参数资料
型号: MAX5165MECM+T
厂商: Maxim Integrated Products
文件页数: 11/12页
文件大小: 0K
描述: IC AMP SAMPLE/HOLD 32CH 48-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
放大器类型: 采样和保持
电路数: 32
电流 - 输入偏压: 1µA
电压 - 输入偏移: 5000µV
电流 - 电源: 36mA
电流 - 输出 / 通道: 2mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 带卷 (TR)
MAX5165
Output Clamp
The MAX5165 clamps the output between two external-
ly applied reference voltages. Internal diodes connect
all outputs to the clamping voltages, restricting the out-
put voltage to:
VCH + 0.7V
≤ VOUT_ ≤ VCL - 0.7V
When the clamping voltage exceeds the maximum out-
put voltage, the maximum output voltage will be the lim-
iting factor. To disable output clamping, connect CH to
VDD and CL to VSS to set the clamping voltages beyond
the maximum output voltage range. The clamping
diodes allow the MAX5165 to be used with other
devices requiring restricted input voltages.
Timing Definitions
Acquisition time (tAQ) is the amount of time the
MAX5165 must remain in sample mode for the hold
capacitor to acquire an accurate sample. The hold-
mode settling time (tH) is the amount of time necessary
for the output voltage to settle to its final value. Aperture
delay (tAP) is the time interval required to disconnect
the input from the hold capacitor. The inhibit pulse
width (tPW) is the amount of time the MAX5165 must
remain in hold mode while the address is changed. The
data setup time (tDS) is the amount of time an address
must be maintained before the address becomes valid.
The data hold time (tDH) is the amount of time that an
address must be maintained after mode select has
gone from low to high (Figure 2).
__________Applications Information
Control-Line Reduction
The MAX5165 contains four separate 1-to-8 multiplex-
ers and individual mode selectors for each multiplexer.
Configure the device to sample only one channel at a
time or up to four channels (with the same address, see
Table 1) simultaneously. When sampling one channel
at a time, use an external 2-to-4 decoder (with active-
low outputs) to reduce the number of digital control
lines from seven to five (Figure 3).
Single vs. Simultaneous Sampling
Individually control the four mode/multiplexer-select
pins to simultaneously sample on four channels, the
same channel for each multiplexer (Figure 4). Each
mode-select pin controls sampling on one of the 1-to-8
multiplexers, while the 3-bit address selects one of the
eight channels on all the multiplexers (Tables 1, 2).
Setting any combination of the mode-select pins low
enables sampling on the addressed channels for the
selected multiplexers.
Simultaneously sampling two or more channels reduces
offset voltage but increases acquisition time. Multiply
the single-channel acquisition time by the number of
channels sampling.
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
8
_______________________________________________________________________________________
MODE
SELECT
ADDRESS
(A0–A2)
OUTPUT
INPUT
tPW
tAQ
tDH
tH
tAP
HOLD STEP
tDS
Figure 2. Timing Performance
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