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参数资料
| 型号： | MAX5191BEEI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/14页 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT DUAL 40MHZ 28-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 设置时间： | 25µs |
| 位数： | 8 |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 28-QSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电压，单极 |
| 采样率（每秒）： | * |
MAX5188/MAX5191
Dual, 8-Bit, 40MHz, Current/Voltage,
Alternate-Phase Output DACs
12
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of the transfer function once offset and gain errors have
been nullified. For a DAC, the deviations are measured
at every single step.
Differential Nonlinearity
Differential nonlinearity (DNL) (Figure 5b) is the differ-
ence between an actual step height and the ideal value
of 1LSB. A DNL error specification of less than 1LSB
guarantees no missing codes and a monotonic transfer
function.
Offset Error
Offset error (Figure 5c) is the difference between the
ideal and the actual offset point. For a DAC, the offset
point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated by trimming.
Gain Error
Gain error (Figure 5d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the noise generated on a DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first four harmonics to the fun-
damental itself. This is expressed as:
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component.
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high input-bandwidth
amplifier may be used to generate a voltage from the
MAX5188’s current-array output. The differential volt-
age across OUT1P (or OUT2P) and OUT1N (or OUT2N)
is converted into a single-ended voltage by designing
an appropriate operational amplifier configuration as
shown in Figure 6.
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influ-
ence the performance of the MAX5188/MAX5191.
Unwanted digital crosstalk may couple through the
input, reference, power-supply, and ground connec-
tions, which may affect dynamic specifications like SNR
or SFDR. In addition, electromagnetic interference
(EMI) can either couple into or be generated by the
MAX5188/MAX5191. Therefore, grounding and power-
supply decoupling guidelines for high-speed, high-fre-
quency applications should be closely followed.
First, a multilayer PC board with separate ground and
power-supply planes is recommended. High-speed
signals should run on controlled impedance lines
directly above the ground plane. Since the MAX5188/
MAX5191 have separate analog and digital ground
buses (AGND and DGND, respectively), the PC board
should also have separate analog and digital ground
sections with only one point connecting the two. Digital
signals should run above the digital ground plane, and
analog signals should run above the analog ground
plane.
Both devices have two power-supply inputs: analog
VDD (AVDD) and digital VDD (DVDD). Each AVDD input
should be decoupled with parallel 10F and 0.1F
ceramic-chip capacitors as close to the pin as possi-
ble. Their opposite ends should have the shortest pos-
sible connection to the ground plane. The DVDD pins
should also have separate 10F and 0.1F capacitors,
again adjacent to their respective pins. Try to minimize
the analog load capacitance for proper operation. For
best performance, bypass CREF1 and CREF2 with low-
ESR, 0.1F capacitors to AVDD.
The power-supply voltages should also be decoupled
with large tantalum or electrolytic capacitors at the
point they enter the PC board. Ferrite beads with addi-
tional decoupling capacitors forming a pi network could
also improve performance.
THD
VVV
V
=×
++
+
()
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