参数资料
型号: MAX5205BEUB+T
厂商: Maxim Integrated Products
文件页数: 9/13页
文件大小: 0K
描述: IC DAC 16BIT SRL 10UMAX
标准包装: 2,500
设置时间: 25µs
位数: 16
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
电压电源: 单电源
功率耗散(最大): 444.4mW
工作温度: -40°C ~ 105°C
安装类型: *
封装/外壳: *
供应商设备封装: *
包装: *
输出数目和类型: 1 电压,单极;1 电压,双极
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in MAX
_______________________________________________________________________________________
5
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (DIN, SCLK,
CS, CLR, LDAC)
Input High Voltage
VIH
2.1
V
Input Low Voltage
VIL
0.6
V
Input Hysteresis
VHYST
200
mV
Input Leakage
IIN
Digital inputs = 0 or VDD
±1
A
Input Capacitance
CIN
15
pF
POWER REQUIREMENTS
Positive Power Supply
VDD
2.7
3.6
V
Positive Supply Current
IDD
All digital inputs at 0 or VDD (Note 5)
0.5
1.5
mA
Shutdown Supply Current
ISHDN
All digital inputs at 0 or VDD
110
A
TIMING CHARACTERISTICS
SCLK Frequency
fSCLK
10
MHz
SCLK Clock Period
tCP
100
ns
SCLK Pulse Width High
tCH
40
ns
SCLK Pulse Width Low
tCL
40
ns
DIN Setup Time
tDS
40
ns
DIN Hold Time
tDH
0ns
CS Fall to SCLK Rise Setup Time
tCSS
40
ns
SCLK Rise to CS Rise Hold Time
tCSH
0ns
SCLK Rise to CS Fall Ignore
tCS0
10
ns
CS Rise to SCLK Rise Ignore
tCS1
40
ns
LDAC Pulse Width
tLDAC
40
ns
CS Rise to LDAC Low Setup
tLDACS
40
ns
SCLK Fall to CS Fall Ignore
tCSOL
10
ns
CS Pulse Width Low for Shutdown
tCSWL
40
ns
CS Pulse Width High
tCSWH
100
ns
Note 1: Static performance tested at VDD = +5.0V (MAX5204/MAX5205) and at VDD = +3.0V (MAX5206/MAX5207).
Note 2: INL and DNL are guaranteed for outputs between 0.5V to (VDD - 0.5V).
Note 3: Guaranteed monotonic.
Note 4: VREF = 4.096V (MAX5204/MAX5205) and VREF = 2.048V (MAX5206/MAX5207).
Note 5: RL =
∞, digital inputs are at VDD or DGND.
ELECTRICAL CHARACTERISTICS—MAX5206/MAX5207 (continued)
(VDD = +2.7V to +3.6V, fSCLK = 10MHz (50% duty cycle), VREF = 2.048V, output load = 10k
in parallel with 250pF, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
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