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参数资料
| 型号： | MAX532 |
| 厂商： | Maxim Integrated Products, Inc. |
| 英文描述： | Dual, Serial-Input, Voltage-Output, 12-Bit MDAC(双通道,串行输入,电压输出,12位D/A转换器) |
| 中文描述： | 双路、串行输入、电压输出、乘法、12位DAC |
| 文件页数： | 4/16页 |
| 文件大小： | 208K |
| 代理商： | MAX532 |
M
Dual, S erial-Input,
Voltage-Output, 12-Bit MDAC
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
= 11.4V to 16.5V, V
= -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, R
L
= 2k
, C
L
= 100pF,
VOUT_ connected to RFB_, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SYMBOL
VREF = 100mV
sine wave;
DAC latch loaded with all 1s
1.0
MHz
VREF = 20V
10kHz sine wave;
DAC latch loaded with all 0s
-77
dB
Full-Power Bandwidth
125
kHz
THD
Total Harmonic Distortion
-90
dB
Output Noise Voltage
0.1Hz to 10Hz
2
μV
RMS
Digital Crosstalk
DACA code all 1s, DACB code transition from all 0s to all 1s
10
nV-s
Digital Feedthrough
CS
= 1; transitions on SCLK,
LDAC
, DIN
1.1
nV-s
PARAMETER
t
CL
t
DS
t
DH
CONDITIONS
MIN
TYP
MAX
SCLK Pulse Width Low
DIN to SCLK Rise Setup Time
UNITS
SYMBOL
f
CLK
t
CH
80
50
0
ns
ns
ns
t
CSS1
t
CSH0
t
CSH1
t
CSW
t
DO
t
DV
t
TR
t
LDAC
t
LDACS
CS
Rise to SCLK Rise Setup Time
SCLK Fall to
CS
Fall Hold Time
SCLK Rise to
CS
Rise Hold Time
CS
Pulse Width High
SCLK Fall to DOUT Valid (Note 6)
CS
Fall to DOUT Enable (Note 7)
CS
Rise to DOUT Disable (Note 7)
LDAC
Pulse Width Low
CS
Rise to
LDAC
Fall Setup Time
Note 4:
All input signals are specified with t
R
= t
F
≤
5ns. Logic input swing is 0V to 5V.
Note 5:
See Figure 1.
Note 6:
Timing is for SCLK fall to DOUT fall to 0.8V, or for SCLK fall to DOUT rise to 2.4V. Additional time must be added for any
larger passive RC pull-up delay.
Note 7:
DOUT enable: DOUT falls to 4.5V from 5.0V. DOUT disable: DOUT rises to 0.5V from 0V.
SCLK Clock Frequency
SCLK Pulse Width High
50
5
80
120
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CSS0
CS
Fall to SCLK Rise Setup Time
6.25
MHz
ns
50
ns
DIN to SCLK Rise Hold Time
80
Multiplying Feedthrough
Error
Unity-Gain Small-Signal
Bandwidth
VREF = 20V
sine wave;
DAC latch loaded with all 1s
VREF = 6V
, 1kHz sine wave;
DAC latch loaded with all 1s
Note 1:
Static performance tested at V
DD
= +15V, V
SS
= -15V. Performance over supplies guaranteed by PSR test.
Note 2:
Guaranteed by design. Not subject to production testing.
Note 3:
Open-drain output.
TIMING CHARACTERISTICS
(V
DD
= 11.4V to 16.5V, V
SS
= -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V) (Notes 4, 5)
C
L
= 20pF, R
PULL-UP
= 1k
to 5V
C
L
= 20pF, R
PULL-UP
= 1k
to 5V
C
L
= 20pF, R
PULL-UP
= 1k
to 5V
200
100
60
60
100
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