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参数资料
| 型号： | MAX532AEWE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/16页 |
| 文件大小： | 0K |
| 描述： | IC MDAC 12BIT DUAL SER 16-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 设置时间： | 2.5µs |
| 位数： | 12 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 双 ± |
| 功率耗散（最大）： | 762mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电压，单极；2 电压，双极 |
| 采样率（每秒）： | * |
With the values of tRC given in Table 1, tCSS0 is always
given by tDV + tDS. For different values of R or C, tRC
must be calculated to determine tCSS0.
Additionally, the maximum clock frequency is limited to
1
fCLK (max) =
————————————— .
2 x (tDO + tRC -15ns + tDS)
For example, with tRC = 15ns (5V ±10% supply with
1k
pull-up), the maximum clock frequency is 2MHz.
Digital-to-Analog Section
Figure 8 shows a simplified circuit diagram for one of
the DACs and the output amplifier.
A segmented scheme is used to improve linearity,
whereby the two MSBs of the 12-bit data word are
decoded to drive the three switches, SA, SB, and SC.
The remaining ten bits drive the switches S0 through S9
in a standard R-2R ladder configuration.
Each of the switches, SA, SB, and SC, steers 1/4 of the
total reference current with the remaining 1/4 passing
through the R-2R section.
The output amplifier and feedback resistor perform the
current-to-voltage conversion, giving the following:
VOUT_ = -D x VREF_,
where _ denotes A or B, and D is the fractional representa-
tion of the digital word. (D can be set from 0 to 4095/4096.)
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
______________________________________________________________________________________
11
VPULL-UP (V)
C (pF)
RP (k)tRC (ns)
4.5
20
1
15
4.5
35
1
27
4.5
50
1
38
4.5
100
1
76
4.5
150
1
114
11.4
20
3
14
11.4
35
3
25
11.4
50
3
35
11.4
100
3
71
11.4
150
3
106
13.5
20
3
12
13.5
35
3
21
13.5
50
3
29
13.5
100
3
59
13.5
150
3
88
Table 1. tRC Delay Times
RR
R
2R
SC
SB
SA
S9
S8
S0
R/2
RFB_
VOUT_
AGND_
SHOWN FOR ALL 1s ON DAC
VREF_
Figure 8. Simplified D/A Circuit Diagram
DACA
AGNDA
VSS
DGND
RFBA
VOUTA
VOUT
VIN
-12V to -15V
VDD
VREFA
+12V to +15V
MAX532
Figure 9. Unipolar Binary Operation
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