参数资料
型号: MAX5361PEUK+T
厂商: Maxim Integrated Products
文件页数: 3/13页
文件大小: 0K
描述: IC DAC 6BIT LP 2WIRE SER SOT23-5
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
设置时间: 20µs
位数: 6
数据接口: I²C,串行
转换器数目: 1
电压电源: 单电源
功率耗散(最大): 571mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SC-74A,SOT-753
供应商设备封装: SOT-23-5
包装: 带卷 (TR)
输出数目和类型: 1 电压,单极
采样率(每秒): *
I2C Compatibility
The MAX5360/MAX5361/MAX5362 are compatible with
existing I2C systems. SCL and SDA are high-imped-
ance inputs; SDA has an open drain that pulls the data
line low during the 9th clock pulse. Figure 7 shows a
typical I2C application. The communication protocol
supports the standard I2C 8-bit communications. The
general call address is ignored, and CBUS formats are
not supported. The MAX5360/MAX5361/MAX5362
address is compatible with the 7-bit I2C addressing
protocol only. No 10-bit formats are supported.
RESTART protocol is supported, but an immediate
STOP condition is necessary to update the DAC.
Applications Information
Digital Inputs and Interface Logic
The serial 2-wire interface has logic levels defined as
VOL = 0.3 x VDD and VOH = 0.7 x VDD. All of the inputs
include Schmitt-trigger buffers to accept slow-transition
interfaces. This means that optocouplers can interface
directly to the MAX5360/MAX5361/MAX5362 without
additional external logic. The digital inputs are compati-
ble with CMOS logic levels and must not be driven with
voltages higher than VDD.
Power-Supply Bypassing and Layout
Careful PC board layout is important for best system
performance. To reduce crosstalk and noise injection,
keep analog and digital signals separate. Ensure that
the ground return from GND to the supply ground is
short and low impedance; a ground plane is recom-
mended. Bypass VDD with a 0.1F to ground as close
as possible to the device. If the supply is excessively
noisy, connect a 10
Ω resistor in series with the supply
and VDD, and add additional capacitance
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
______________________________________________________________________________________
11
μC
SDA SCL
VDD
OFFSET ADJUSTMENT
THRESHOLD ADJUSTMENT
GAIN ADJUSTMENT
SCL
SDA
VDD
OUT
MAX5360L
2V REFERENCE
SCL
SDA
VDD
OUT
MAX5361M
4V REFERENCE
SCL
SDA
VDD
OUT
MAX5362P
VDD REFERENCE
Figure 7. I2C Typical Application
PROCESS: BiCMOS
Chip Information
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