参数资料
型号: MAX5426CEUD+
厂商: Maxim Integrated Products
文件页数: 3/9页
文件大小: 0K
描述: IC INSTR AMP PROGR PREC 14-TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 96
系列: *
类型: *
应用: *
安装类型: 表面贴装
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 14-TSSOP
包装: 管件
MAX5426
Precision Resistor Network for
Programmable Instrumentation Amplifiers
_______________________________________________________________________________________
3
Note 1: Total error when configured as instrumentation amplifier. Assumes ideal op amps.
Note 2: Each stage (input stage and output stage) is tested for accuracy separately and combined to give the total gain accuracy.
The input stage is tested as follows: OUT1 = 10V, OUT2 = 0. Output stage is tested as follows OUT1 = 10V, OUT2 = 0 and
OUT2 = 10V, OFFSET = 0.
Note 3: Gain of 1 configuration is open circuit (infinite impedance).
Note 4: Equivalent load at each pin is calculated according to instrumentation amplifier configuration and assumes ideal op amps.
Note 5: See Timing Diagram.
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +15V, VSS = -15V, GND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Gain = 2
29
Gain = 4
15
Resistance Between FB1 and FB2
(Note 3)
RFB1, RFB2
Gain = 8
7
k
Gain = 1
0
Gain = 2
15
Gain = 4
22
Resistance Between OUT2 and
FB2
ROUT2, RFB2
Gain = 8
26
k
Input Impedance at FB1
ZFB1
0k
Input Impedance at FB2
ZFB2
0k
Gain = 1
0
Gain = 2
9.5
Gain = 4
12
Input Impedance at OUT1
(Note 4)
ZOUT1
Gain = 8
13
k
Gain = 1
0
Gain = 2
9.5
Gain = 4
12
Input Impedance at OUT2
(Note 4)
ZOUT2
Gain = 8
13
k
Input Impedance at INDIF+
(Note 4)
ZINDIF+
0k
Input Impedance at INDIF-
(Note 4)
ZINDIF-
0k
Input Impedance at OUT (Note 4)
ZOUT
26
k
Input Impedance at OFFSET
(Note 4)
ZOFFSET
26
k
POWER REQUIREMENTS
Positive Power-Supply Voltage
VDD
4.75
15.75
V
Negative Power-Supply Voltage
VSS
-15.75
-4.75
V
D1 = D0 = 0
10
Positive Supply Current
IDD
D1 = D0 = 5V
36
80
A
Negative Supply Current
ISS
0.01
10
A
TIMING REQUIREMENTS
Switching Time (Note 5)
tSWITCHING
(Figure 3)
60
ns
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