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| 型号： | MAX5443BCUA+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 6/12页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT 3V SERIAL 8-UMAX |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 设置时间： | 1µs |
| 位数： | 16 |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 362mW |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-uMAX |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电压，单极 |
MAX5441–MAX5444
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
_______________________________________________________________________________________
3
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.3V (MA5443/MAX5444) , VDD = +4.5V to +5.5V (MAX5441/MAX5442), VREF = +2.5V, GND = 0, CMOS inputs,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Figure 1)
Note 1: Gain error tested at VREF = +2.0V, +2.5V, and +3.0V (MAX5443/MAX5444) or VREF = +2.0V, +2.5V, +3.0V, and +5.5V
(MAX5441/ MAX5442).
Note 2: ROUT tolerance is typically ±20%.
Note 3: Min/max range guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.
Note 4: Reference input resistance is code-dependent, minimum at 8555hex in unipolar mode, 4555hex in bipolar mode.
Note 5: Slew-rate value is measured from 10% to 90%.
Note 6: Guaranteed by design. Not production tested.
Note 7: Guaranteed by power-supply rejection test and
Timing Characteristics.
All digital inputs at
VDD or GND
All digital inputs at VDD or GND
MAX5443/MAX5444
Code = 0000 hex, VREF = 1VP-P at 100kHz
Code = 0000 hex
Code = FFFF hex
(Note 6)
CONDITIONS
mW
0.36
PD
Power Dissipation
mA
0.12
0.20
IDD
Positive Supply Current
V
2.7
3.6
VDD
Positive Supply Range (Note 7)
V
0.15
VH
Hysteresis Voltage
pF
310
CIN
Input Capacitance
mVP-P
1
A
±1
IIN
Input Current
V
0.8
VIL
Input Low Voltage
V
2.4
VIH
Input High Voltage
Reference Feedthrough
dB
92
SNR
Signal-to-Noise Ratio
70
pF
170
CINREF
Reference Input Capacitance
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
(Note 6)
CONDITIONS
s
20
VDD High to CS Low
(power-up delay)
ns
20
tCL
SCLK Pulse Width Low
ns
20
tCH
MHz
25
fCLK
SCLK Frequency
SCLK Pulse Width High
ns
20
tCLW
CLR Pulse Width Low
ns
0
tDH
DIN to SCLK High Hold
ns
15
tDS
DIN to SCLK High Setup
ns
15
tCSS0
CS Low to SCLK High Setup
ns
15
tCSS1
CS High to SCLK High Setup
ns
35
tCSH0
SCLK High to CS Low Hold
ns
20
tCSH1
SCLK High to CS High Hold
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Code = FFFF hex
MHz
1
BW
Reference -3dB Bandwidth
MAX5441/MAX5442
4.5
5.5
0.60
DYNAMIC PERFORMANCE—REFERENCE SECTION
STATIC PERFORMANCE—DIGITAL INPUTS
POWER SUPPLY
MAX5441/MAX5442
MAX5443/MAX5444
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3V (MAX5443/MAX5444) or +5V (MAX5441/MAX5442), VREF = +2.5V, CL = 10pF, GND = 0, RL = ∞, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
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