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参数资料
| 型号： | MAX547AEMH+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/16页 |
| 文件大小： | 0K |
| 描述： | IC DAC 13BIT OCTAL PAR 44-MQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 500 |
| 设置时间： | 5µs |
| 位数： | 13 |
| 数据接口： | 并联 |
| 转换器数目： | 8 |
| 电压电源： | 双 ± |
| 功率耗散（最大）： | 889mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-QFP |
| 供应商设备封装： | 44-MQFP（10x10） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 8 电压，单极；8 电压，双极 |
| 采样率（每秒）： | * |
Reference and Analog-Ground Inputs
The REF_ inputs can range between AGND_ and VDD.
However, the DAC outputs will operate to VDD - 0.6V
and VSS + 0.6V, due to the output amplifiers’ voltage-
swing limitations. The AGND_ inputs can be offset by
any voltage within the supply rails. The offset-voltage
potential must be lower than the reference-voltage
potential. For more information, refer to the
Digital Code
and
Analog Output Voltage section in the Applications
Information.
The input impedance of the REF_ inputs is code depen-
dent. It is at its lowest value (5k
min) when the input
code of the referring DAC pair is 0 1010 1010 1010
(0AAAhex). Its maximum value, typically 50k
, occurs
when the code is 0000hex. When all reference inputs are
driven from the same source, the minimum load imped-
ance is 1.25k
. Since the input impedance at REF_ is
code dependent, load regulation of the reference used is
important. For more information, see
Reference
Selection in the Applications Information section.
The input capacitance at REF_ is also code dependent,
and typically varies from 125pF to 300pF. Its minimum
value occurs when the code of the referring DAC pair is
set to all 0s. It is at its maximum value with all 1s on both
DACs.
Output Buffer Amplifiers
The MAX547’s voltage outputs are internally buffered
by precision gain-of-two amplifiers with a typical slew
rate of 3V/s. With a full-scale transition at its output,
the typical settling time to ±12LSB is 5s when loaded
with 10k
in parallel with 50pF, or 6s when loaded
with 10k
in parallel with 100pF.
Digital Inputs and Interface Logic
All digital inputs are compatible with both TTL and
CMOS logic. The MAX547 interfaces with microproces-
sors using a data bus at least 13 bits wide. The inter-
face is double buffered, allowing simultaneous update
of all DACs. There are two latches for each DAC (see
Functional Diagram): an input latch that receives data
from the data bus, and a DAC latch that receives data
from the input latch. Address lines A0, A1, and A2
select which DAC’s input latch receives data from the
data bus, as shown in Table 1. Transfer data from the
input latches to the DAC latches by asserting the asyn-
chronous LD_ signal. Each DAC’s analog output
reflects the data held in its DAC latch. All control inputs
are level triggered.
Data can be latched or transferred directly to the DAC.
CS and WR control the input latch and LD_ transfers
information from the input latch to the DAC latch. The
input latch is transparent when CS and WR are low, and
the DAC latch is transparent when LD_ is low. The
address lines (A0, A1, A2) must be valid throughout the
time CS and WR are low (Figure 3). Otherwise, the data
can be inadvertently written to the wrong DAC. Data is
latched within the input latch when either CS or WR is
high. Taking LD_ high latches data into the DAC latches.
If LD_ is brought low when WR and CS are low, it must
be held low for t3 or longer after WR and CS are high
(Figure 3).
Pulling the asynchronous CLR input low sets all DAC
outputs to a nominal 0V, regardless of the state of CS,
WR, and LD_. Taking CLR high latches 1000hex into
all input latches and DAC latches.
Table 1. MAX547 DAC Addressing
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
8
_______________________________________________________________________________________
TO INPUT LATCH OF DAC H
TO INPUT LATCH OF DAC G
TO INPUT LATCH OF DAC F
TO INPUT LATCH OF DAC E
TO INPUT LATCH OF DAC D
TO INPUT LATCH OF DAC C
TO INPUT LATCH OF DAC B
TO INPUT LATCH OF DAC A
TO DAC LATCHES OF DAC G AND DAC H
TO DAC LATCHES OF DAC E AND DAC G
TO DAC LATCHES OF DAC C AND DAC D
TO DAC LATCHES OF DAC C AND DAC B
TO ALL INPUT AND DAC LATCHES
A2
A1
A0
LDGH
LDEF
LDCD
LDAB
CLR
WR
CS
Figure 2. Input Control Logic
A0
A2
FUNCTION
0
DAC A input latch
1
0
DAC D input latch
1
0
DAC B input latch
0
DAC C input latch
0
A1
0
1
0
1
DAC E input latch
1
DAC F input latch
1
0
1
DAC G input latch
1
DAC H input latch
1
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相关代理商/技术参数 |
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| MAX547AEQH | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube 制造商:Rochester Electronics LLC 功能描述: |
| MAX547AEQH+D | 功能描述:数模转换器- DAC 13-Bit 8Ch Precision DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| MAX547AEQH+TD | 功能描述:数模转换器- DAC 13-Bit 8Ch Precision DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| MAX547AEQH-D | 功能描述:数模转换器- DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| MAX547AEQH-TD | 功能描述:数模转换器- DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
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