参数资料
型号: MAX5531ETC+T
厂商: Maxim Integrated Products
文件页数: 10/19页
文件大小: 0K
描述: IC DAC 12BIT SGL ULP 12-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
设置时间: 660µs
位数: 12
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
电压电源: 单电源
功率耗散(最大): 1.35mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 12-WQFN 裸露焊盘
供应商设备封装: 12-TQFN-EP(4x4)
包装: 带卷 (TR)
输出数目和类型: 1 电压,单极;1 电压,双极
采样率(每秒): *
MAX5530/MAX5531
Ultra-Low-Power, 12-Bit,
Voltage-Output DACs
18
______________________________________________________________________________________
Power Supply and Bypassing
Considerations
Bypass the power supply with a 0.1F capacitor to GND.
Minimize lengths to reduce lead inductance. If noise
becomes an issue, use shielding and/or ferrite beads to
increase isolation. For the thin QFN package, connect
the exposed paddle to ground.
Layout Considerations
Digital and AC transient signals coupling to GND can
create noise at the output. Use proper grounding tech-
niques, such as a multilayer board with a low-inductance
ground plane. Wire-wrapped boards and sockets are not
recommended. For optimum system performance, use
printed circuit (PC) boards. Good PC board ground lay-
out minimizes crosstalk between DAC outputs, reference
inputs, and digital inputs. Reduce crosstalk by keeping
analog lines away from digital lines.
Figure 8. Bipolar Output Circuit
Figure 9. Separate Force-Sense Outputs Create Unity and
Greater-than-Unity DAC Gains Using the Same Reference
REFIN
MAX5530
OUT
VOUT
FB
V+
10k
V-
DAC
REFIN
VOUT
OUT
MAX5530
FB
R2
R1
DAC
Figure 10. Software-Configurable Output Gain
H
L
FB
W
NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
NPOT IS THE NUMERIC VALUE OF THE POT INPUT CODE.
REFIN
MAX5530
MAX5401
SOT-POT
100k
VOUT
5PPM/°C
RATIOMETRIC
TEMPCO
1.8V ≤ VDD ≤ 5.5V
VOUT
VOUT =
VREFIN × NDAC
4096
(1 +
255 - NPOT)
255
SCLK
DIN
CS2
CS1
DAC
Chip Information
TRANSISTOR COUNT: 10,688
PROCESS: BiCMOS
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