参数资料
型号: MAX5631UCB+TD
厂商: Maxim Integrated Products
文件页数: 15/15页
文件大小: 0K
描述: IC DAC 16BIT 32CH S&H 64-TQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 750
位数: 16
数据接口: 串行
转换器数目: 32
电压电源: 双 ±
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 带卷 (TR)
输出数目和类型: 32 电压,单极
采样率(每秒): *
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
9
Maxim Integrated
Detailed Description
Digital-to-Analog Converter
The MAX5631/MAX5632/MAX5633 16-bit digital-to-ana-
log converters (DAC) are composed of two matched
sections. The four MSBs are derived through 15 identi-
cal matched resistors and the lower 12 bits are derived
through a 12-bit inverted R-2R ladder.
Sample-and-Hold Amplifiers
The MAX5631/MAX5632/MAX5633 contain 32 buffered
sample/hold circuits with internal hold capacitors.
Internal hold capacitors minimize leakage current,
dielectric absorption, feedthrough, and required board
space. MAX5631/MAX5632/MAX5633 provide a very low
1mV/s droop rate.
Output
The MAX5631/MAX5632/MAX5633 include output buffers
on each channel. The device contains output resistors in
series with the buffer output (Figure 3) for ease of output
filtering and capacitive load driving stability.
Output loads increase the analog supply current (IDD
and ISS). Excessively loading the outputs drastically
increases power dissipation. Do not exceed the maxi-
mum power dissipation specified in the
Absolute
Maximum Ratings.
The maximum output voltage range depends on the
analog supply voltages available and the output clamp
voltages (see
Output Clamp).
The device has a fixed theoretical output range deter-
mined by the reference voltage, gain, and midscale offset.
The output voltage for a given input code is calculated
with the following:
where code is the decimal value of the DAC input
code, VREF is the reference voltage, and VGS is the
V
code
V
OUT
REF
GS
=
××
×
()+
65535
5 2428
.-
1.6214 VREF
VV
V
SS
OUT
DD
+
()≤≤()
075
24
..
_
-
Table 1. Code Table
DAC INPUT CODE
MSB
LSB
NOMINAL OUTPUT
VOLTAGE (V)
VREF = +2.5V
1111 1111 1111 1111
9.0535
Full-scale output
1100 0111 0100 1010
6.15
Maximum output with VDD = 8.55V
1000 0000 0000 0000
2.5
Midscale output
0100 1111 0010 1100
0
VOUT_ = 0. All outputs default to this code after power-up
0010 1000 0001 1100
-2.0
Minimum output with VSS = -2.75V
0000 0000 0000 0000
-4.0535
Zero-scale output
tCSHO
tCH
tCSSO
tCL
tDH
tDS
tCSH1
tCSS1
CS
SCLK
DIN
B23
B22
B0
Figure 2. Serial Interface Timing Diagram
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