参数资料
型号: MAX5856AECM+D
厂商: Maxim Integrated Products
文件页数: 20/23页
文件大小: 0K
描述: IC DAC 8BIT DUAL 300MSPS 48-TQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 250
设置时间: 11ns
位数: 8
数据接口: 并联
转换器数目: 2
电压电源: 单电源
功率耗散(最大): 792mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-TQFP 裸露焊盘
供应商设备封装: 48-TQFP 裸露焊盘(7x7)
包装: 托盘
输出数目和类型: 2 电流,单极
采样率(每秒): 300M
MAX5856A
Dual 8-Bit, 300Msps DAC with 4x/2x/1x
Interpolation Filters and PLL
6
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, fDAC = 165Msps, no interpolation, PLL disabled, external reference,
VREFO = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25°C,
guaranteed by production test. TA < +25°C, guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
No interpolation
43
2x interpolation
99
fDAC = 60Msps
4x interpolation
104
No interpolation
53
58
2x interpolation
147
fDAC = 165Msps
4x interpolation
147
2x interpolation
165
178
Digital Supply Current (Note 4)
IDVDD
fDAC = 200Msps
4x interpolation
162
175
mA
PLL Power-Supply Voltage
PVDD
2.7
3.3
V
fDAC = 60Msps
16
fDAC = 165Msps
47
50
PLL Supply Current (Note 4)
IPVDD
fDAC = 200Msps, 2x interpolation or 4x
interpolation
55
60
mA
Standby Current
ISTANDBY
(Note 5)
4.4
4.8
mA
Power-Down Current
IPD
(Note 5)
1
A
No interpolation
309
2x interpolation
477
fDAC = 60Msps
4x interpolation
492
No interpolation
432
456
2x interpolation
714
fDAC = 165Msps
4x interpolation
714
2x interpolation
792
Total Power Dissipation
(Note 4)
PTOT
fDAC = 200Msps
4x interpolation
783
mW
Note 1: Including the internal reference voltage tolerance.
Note 2: Measured single ended with 50 load and complementary output connected to ground.
Note 3: Guaranteed by design, not production tested.
Note 4: Tested with an output frequency of fOUT = 5MHz.
Note 5: All digital inputs at 0 or DVDD. Clock signal disabled.
1.6V
5pF
TO OUTPUT PIN
0.5mA
Figure 1. Load Test Circuit for CLK Outputs
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