参数资料
型号: MAX5877EGK+D
厂商: Maxim Integrated Products
文件页数: 19/19页
文件大小: 0K
描述: IC DAC 14BIT DUAL 250MSPS 68-QFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 30
设置时间: 14ns
位数: 14
数据接口: 并联
转换器数目: 2
电压电源: 模拟和数字
功率耗散(最大): 331mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 68-VFQFN 裸露焊盘
供应商设备封装: 68-QFN 裸露焊盘(10x10)
包装: 管件
输出数目和类型: 4 电流,单极
采样率(每秒): 250M
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
_______________________________________________________________________________________
9
Pin Description
PIN
NAME
FUNCTION
1
B2N
Complementary Data Bit 2
2
B1P
Data Bit 1
3
B1N
Complementary Data Bit 1
4
B0P
Data Bit 0 (LSB)
5
B0N
Complementary Data Bit 0 (LSB)
6–9
N.C.
No Connection. Leave floating or connect to GND.
10, 12, 13, 15,
20, 23, 26, 27,
30, 33, 36
GND
Ground
11
DVDD3.3
Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1F
capacitor to GND.
14, 21, 22, 31,
32
AVDD3.3
Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass each pin with
a 0.1F capacitor to GND.
16
REFIO
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1F
capacitor to GND. REFIO can be driven with an external reference source. See Table 1.
17
FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full-
scale output current, connect a 2k
resistor between FSADJ and DACREF. See Table 1.
18
DACREF
Current-Set Resistor Return Path. Internally connected to GND. Do not use as an external
ground connection.
19, 34
AVDD1.8
Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass each pin with a
0.1F capacitor to GND.
24
OUTQN
Complementary Q-DAC Output. Negative terminal for current output.
25
OUTQP
Q-DAC Output. Positive terminal for current output.
28
OUTIN
Complementary I-DAC Output. Negative terminal for current output.
29
OUTIP
I-DAC Output. Positive terminal for current output.
35
AVCLK
Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1F
capacitor to GND.
37
CLKN
Complementary Converter Clock Input. Negative input terminal for LVDS/LVPECL-compatible
differential converter clock. Internally biased to AVCLK / 2.
38
CLKP
Converter Clock Input. Positive input terminal for LVDS/LVPECL-compatible differential converter
clock. Internally biased to AVCLK / 2.
39
TORB
Two’s-Complement/Binary Select Input. Set TORB to a CMOS-logic-high level to indicate a two’s-
complement input format. Set TORB to a CMOS-logic-low level to indicate an offset binary input
format. TORB has an internal pulldown resistor.
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