参数资料
型号: MAX5898EGK+D
厂商: Maxim Integrated Products
文件页数: 3/33页
文件大小: 0K
描述: IC DAC 16BIT DUAL 500MSPS 68-QFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 30
设置时间: 11ns
位数: 16
数据接口: 并联
转换器数目: 2
电压电源: 模拟和数字
功率耗散(最大): 831mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 68-VFQFN 裸露焊盘
供应商设备封装: 68-QFN 裸露焊盘(10x10)
包装: 管件
输出数目和类型: 2 电流,单极
采样率(每秒): 500M
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
______________________________________________________________________________________
11
Pin Description (continued)
PIN
NAME
FUNCTION
35
D3N
Complementary LVDS Data Bit 3. Internal 110
termination to D3P.
36
D3P
LVDS Data Bit 3. Internal 110
termination to D3N.
38
D2N
Complementary LVDS Data Bit 2. Internal 110
termination to D2P.
39
D2P
LVDS Data Bit 2. Internal 110
termination to D2N.
40
D1N
Complementary LVDS Data Bit 1. Internal 110
termination to D1P.
41
D1P
LVDS Data Bit 1. Internal 110
termination to D1N.
42
D0N
Complementary LVDS Data Bit 0 (LSB). Internal 110
termination to D0P.
43
D0P
LVDS Data Bit 0 (LSB). Internal 110
termination to D0N.
44
DVDD3.3
I/O Power Supply. Accepts a 3.0V to 3.6V supply range. Bypass with a 0.1F capacitor as close to
the pin as possible.
45
DOUT
Serial-Port Data Output
46
DIN
Serial-Port Data Input
47
SCLK
Serial-Port Clock Input. Data on DIN is latched on the rising edge of SCLK.
48
CS
Serial-Port Interface Select. Drive CS low to enable serial-port interface.
49
RESET
Reset Input. Hold RESET low during power-up.
50
REFIO
Reference Input/Output. Bypass to ground with a 1F capacitor as close to the pin as possible.
51
DACREF
Current-Set Resistor Return Path. For a 20mA full-scale output current, use a 1.25V external reference
and connect a 2k
resistor between FSADJ and DACREF. Internally connected to GND. DO NOT USE
AS AN EXTERNAL GROUND CONNECTION.
52
FSADJ
Full-Scale Adjust Input. For a 20mA full-scale output current, use a 1.25V external reference and
connect a 2k
resistor between FSADJ and DACREF.
53, 67
AVDD1.8
Low Analog Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to GND with
a 0.1F capacitor as close to the pin as possible.
54, 56, 59, 61,
64, 66
GND
Ground
55, 60, 65
AVDD3.3
Analog Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass each pin to GND with a
0.1F capacitor as close to the pin as possible.
57
OUTQN
Inverting Differential DAC Current Output for Q Channel
58
OUTQP
Noninverting Differential DAC Current Output for Q Channel
62
OUTIN
Inverting Differential DAC Current Output for I Channel
63
OUTIP
Noninverting Differential DAC Current Output for I Channel
68
AVCLK
Clock Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass to ground with a 0.1F
capacitor as close to the pin as possible.
EP
Exposed Paddle. Must be connected to GND through a low-impedance path.
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