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参数资料
| 型号： | MAX5917BESE+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 9/11页 |
| 文件大小： | 273K |
| 描述： | IC HOT-SWAP SWITCH 65V 16-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | Simple Swapper™ |
| 类型： | 热交换开关 |
| 应用： | IP 电话，LAN 网络供电，网络路由器和交换机 |
| 内部开关： | 是 |
| 电流限制： | 420mA |
| 电源电压： | 10 V ~ 65 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
+65V Simple Swapper Hot-Swap Switches
_______________________________________________________________________________________ 9
Thermal Shutdown Fault
The MAX5910/MAX5917 monitor their internal die tem-
perature. If the temperature of the die exceeds +140癈,
the internal FET is turned off and IFAULT and PGOOD
are pulled low. The output is enabled again only when
the die temperature is below the thermal shutdown tem-
perature by 3.5癈 typically.
Power-Good (PGOOD)
Power-good (PGOOD) logic output signals when the
output has exceeded the PGOOD threshold. When the
output voltage is below 70% of the input voltage,
PGOOD is pulled low. When the output voltage is larger
than 80% of the input voltage for more than 12ms,
PGOOD is asserted.
Applications Information
Choosing a Device
The MAX5910 can output 280mA, the MAX5917B can
output 420mA, and the MAX5917A can output up to
567mA. In applications where high power is expected,
use the MAX5917 for its superior heat dissipation prop-
erties, and always solder all of its GND pins to a large
section of circuit board copper.
Logic Control
The enable input (ENABLE) responds to 3.3V logic sig-
nals and will force the internal FET off if ENABLE is
pulled low. This feature allows the host to disconnect
the load from the power bus if required. Drive ENABLE
high to enable V
OUT
.
Changing the Undervoltage Lockout
Setting
The undervoltage lockout (UVLO) value defaults to
26.5V if the UVLO pin is left open circuit (Figure 3).
Connect UVLO to V
IN
to set the undervoltage lockout to
a minimum of 7.5V (Figure 4). This lockout voltage can
also be changed with a resistive-divider from V
IN
to
GND. The center node of the divider is connected to
the UVLO pin (Figure 5). The values of R1 and R2 must
satisfy the condition R1//R2 << 260k& and R2 <<
1.65M&. R2 can be calculated as follows:
R2 = R1 [(V
UVLO
/ 7.5V) - 1]
where V
IN (UVLO)
is the desired lockout voltage.
+3.3V
IFAULT
V
IN
V
IN
ENABLE
GND
V
OUT
V
OUT
N.C.
PGOOD
UVLO
R
R
MAX5910
+3.3V
V
IN
V
IN
ENABLE
GND
V
OUT
V
OUT
N.C.
PGOOD
UVLO
10k&
10k&
MAX5910
IFAULT
0.1礔
Figure 3. UVLO is Set Internally to its +26.5V Default Value
Figure 4. Minimum +7.5V UVLO Configuration
+3.3V
IFAULT
V
IN
V
IN
ENABLE
GND
V
OUT
V
OUT
N.C.
PGOOD
UVLO
10k&
R1
R2
10k&
MAX5910
0.1礔
Figure 5. Adjusting UVLO with an External Resistive-Divider
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