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参数资料
| 型号： | MAX5929BEEG+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 3/23页 |
| 文件大小： | 340K |
| 描述： | IC HOT SWAP CTLR QUAD 24QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 1 V ~ 15 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 带卷 (TR) |
Low-Voltage, Quad, Hot-Swap
Controllers/Power Sequencers
______________________________________________________________________________________________________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
IN_
= +1V to +15V provided at least one supply is larger than or equal to +2.7V, T
A
= -40癈 to +85癈, unless otherwise noted.
Typical values are at V
IN1
= 12.0V, V
IN2
= 5.0V, V
IN3
= 3.3V, V
IN4
= 1.0V, V
ON_
= +3.3V, and T
A
= +25癈.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MOSFET DRIVER
R
TIM
= 100k?/DIV>
8.0
10.8
13.6
R
TIM
= 4k?(minimum value)
0.30
0.4
0.55
Startup Period (Note 5)
t
START
TIM floating (default)
5
9
14
ms
Charging, V
GATE_
= GND, V
IN_
= 5V
(Note 6)
80
100
125
Discharging, during startup
100
礎
Discharging, normal turn-off or triggered by
the slow comparator after startup,
V
GATE_
= 5V, V
IN_
= 10V, V
ON_
= 0V
2
3
7
Average Gate Current
I
GATE
Discharging, triggered by a fault after
startup, V
GATE_
= 5V, V
IN_
= 10V,
(V
IN_
- V
SENSE_
) > V
FC,TH
(Note 7)
28
50
120
mA
Gate-Drive Voltage
V
DRIVE
V
GATE_
- V
IN_
, I
GATE_
= 1礎
4.9
5.3
5.6
V
ON COMPARATOR
Low to high
0.83
0.875
0.90
V
ON_ Threshold
V
ON_ TH
Hysteresis
25
mV
ON_ Propagation Delay
10mV overdrive
10
祍
ON_ Voltage Range
V
ON_
Without false output inversion
V
IN
V
ON_ Input Bias Current
I
BON_
V
ON_
= V
IN
0.03
1
礎
ON_ Pulse Width Low
t
UNLATCH
To unlatch after a latched fault
100
祍
DIGITAL OUTPUTS (STAT_)
Output Leakage Current
V
STAT_
d 15V
1
礎
Output Voltage Low
V
OL_
POL = unconnected (MAX5927A),
I
SINK
= 1mA
0.4
V
UNDERVOLTAGE LOCKOUT (UVLO)
UVLO Threshold
V
UVLO
Startup is initiated when this threshold is
reached by any V
IN_
and V
ON_
> 0.9V
(Note 8)
2.25
2.65
V
UVLO Hysteresis
V
UVLO HYST
250
mV
UVLO Glitch Filter Reset Time
t
D, GF
V
IN
< V
UVLO
maximum pulse width to reset
10
祍
UVLO to Startup Delay
t
D,UVLO
Time input voltage must exceed V
UVLO
before startup is initiated
20
37.5
60
ms
Input Power-Ready Threshold
V
PWRRDY
(Note 9)
0.9
0.95
1.0
V
Input Power-Ready Hysteresis
V
PWRHYST
50
mV
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