参数资料
型号: MAX5950ETJ+T
厂商: Maxim Integrated
文件页数: 20/28页
文件大小: 552K
描述: IC PWM CTRL HOT-SW 12V 32TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 热交换控制器
应用: 通用型,PCI Express?
内部开关:
电源电压: 8 V ~ 16 V,±5V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
12V PWM Controller with Hot-Swap
20   ______________________________________________________________________________________
Compensation when f
C
< f
ZESR
Figure 6 shows the error-amplifier feedback, as well as its
gain response for circuits that use low-ESR output capac-
itors (ceramic). In this case, f
C
occurs before f
ZESR
.
f
Z1
is set to 0.5 x f
LC
and f
Z2
is set to f
LC
to compen-
sate for the gain-and-phase loss due to the double
pole. Choose the inductor (L) and output capacitor
(C
OUT
) as described in the Inductor Selection and
Output-Capacitor Selection sections.
Pick a value for feedback resistor R5 in Figure 6 (values
between 1k& and 10k& are adequate). C7 is then cal-
culated as:
f
C
occurs between f
Z2
and f
P2
. The circuit is imple-
mented with C7 > C8 and R3 > R6, in which case the
error-amplifier gain (G
EA
) at f
C
is due primarily to C6
and R5. Therefore:
The modulator gain at f
C
is:
Since G
EA(fC)
x G
MOD(fC)
= 1, C6 is calculated by:
R3 is then calculated as:
f
P2
is set at 1/2 the switching frequency (f
SW
). R6 is
then calculated by:
f
P3
is set at 5xf
C
. Therefore, C8 is calculated as:
Compensation when f
C
> f
ZESR
For larger ESR capacitors such as tantalum and alu-
minum electrolytic, f
ZESR
can occur before f
C
. If f
C
>
f
ZESR
, f
C
occurs between f
P2
and f
P3
. f
Z1
and f
Z2
remain the same as before; however, f
P2
is now set
equal to f
ZESR
. The output capacitors ESR zero fre-
R
f
8
1
2
5  5
=
?nbsp  ?nbsp ?/DIV>
?/DIV>
C
f
SW
6
1
2
6  0 5
=
?nbsp   ?/DIV>
?/DIV>
.
R
f
C
LC
3
1
2
6
H
?nbsp   ?/DIV>
?/DIV>
C
f   L  C
R   G
C
OUT
MOD DC
6
2
5
=
?nbsp ?/DIV>
?/DIV>
?/DIV>
?/DIV>
(    )
G
G
L  C
f
MOD fC
MOD DC
OUT    C
(   )
(    )
(   )
=
?nbsp ?/DIV>
?/DIV>
2
2
2
?/DIV>
G
f   C   R
EA fc
C
(  )
=    ?nbsp  ?nbsp   ?/DIV>
2
6   5
?/DIV>
f
R
LC
7
1
2    0 5
5
=
?nbsp   ?nbsp   ?/DIV>
?nbsp  .
GAIN
(dB)
V
OUT
REF
R3
COMP
R6
R5
C6
R4
FREQUENCY
CLOSED-LOOP
GAIN
EA
GAIN
f
Z1
f
Z2
f
C
f
P2
f
P3
C8
EA
C7
Figure 7. Error-Amplifier Compensation Circuit (Closed-Loop
and Error-Amplifier Gain Plot) for Higher ESR Output Capacitors
GAIN
(dB)
V
OUT
REF
R3
COMP
R6
R5
C6
R4
FREQUENCY
CLOSED-LOOP
GAIN
EA
GAIN
f
Z1
f
Z2
f
C
f
P2
f
P3
C8
EA
C7
Figure 6. Error Amplifier Compensation Circuit (Closed-Loop
and Error-Amplifier Gain Plot) for Ceramic Capacitors
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