参数资料
型号: MAX5951ETJ+
厂商: Maxim Integrated Products
文件页数: 11/25页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1MHz
占空比: 88%
电源电压: 4.5 V ~ 16 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 管件
12V/5V Input Buck PWM Controller
Pin Description (continued)
PIN
24
25
26
27
28
29
30
31
32
EP
NAME
CS+
CS-
PGND
DL
DREG
LX
DH
BST
REG
EP
FUNCTION
Positive Current-Sense Input. Connect CS+ to the synchronous MOSFET source (connected to
PGND).
Negative Current-Sense Input. Connect CS- to the synchronous MOSFET drain (connected to LX).
Power-Ground Connection. Connect the input filter capacitor’s negative terminal, the source of the
synchronous MOSFET, and the output filter capacitor’s return to PGND. Connect externally to AGND
at a single point near the input capacitor return terminal.
Low-Side Gate-Driver Output. DL is the gate-driver output for the synchronous MOSFET.
Gate-Drive Supply for the Low-Side MOSFET Driver. Connect externally to REG and the anode of the
boost diode.
Source Connection of the High-Side MOSFET and Drain Connection of the Synchronous MOSFET.
Connect the inductor and the negative side of the boost capacitor to LX.
High-Side Gate-Driver Output. DH drives the gate of the high-side MOSFET.
High-Side Gate-Driver Supply. Connect BST to the cathode of the boost diode and to the positive
terminal of the boost capacitor.
5V Regulator Output. Bypass with a 2.2μF ceramic capacitor to AGND.
Exposed Pad. Connect the exposed pad to AGND.
Detailed Description
The MAX5951 is a PWM, step-down, DC-DC controller.
The device operates over the input-voltage range of 8V
to 16V or 5V ±10% (V IN = V REG ) and provides an
adjustable output from 0.8V to 5.5V. The device deliv-
ers up to 10A of load current with excellent load-and-
line regulation.
The MAX5951 PWM controller utilizes a voltage-mode
control scheme for good noise immunity and offers
external compensation allowing for maximum flexibility
with a wide selection of inductor values and capacitor
types. The device operates at a fixed switching fre-
quency that is programmable from 100kHz to 1MHz
and can be synchronized to an external clock signal
through the SYNC input. The device includes UVLO
and digital soft-start. Protection features include valley-
mode current limit, hiccup-mode output short-circuit
protection, and thermal shutdown.
PWM Controller
PWM UVLO
V IN must exceed the default PWM UVLO threshold (7V
typ) before any PWM operation can commence. The
UVLO circuitry keeps the MOSFET drivers, oscillator,
and all the internal circuitry shut down to reduce cur-
rent consumption.
Override the internal PWM UVLO divider by connecting
an external resistive divider from IN to PUVLO to AGND.
The PUVLO threshold is 1.220V with 122mV hysteresis.
Digital Soft-Start
The MAX5951 soft-start feature allows the load voltage
to ramp up in a controlled manner, eliminating output
voltage overshoot. Soft-start begins after V IN exceeds
the UVLO threshold. The soft-start circuitry gradually
ramps up the reference voltage. This controls the rate
of rise of the output voltage and reduces input surge
currents during startup. The soft-start duration is 1024
clock cycles. The output voltage is incremented
through 128 equal steps. The output reaches regulation
when soft-start is completed, regardless of output
capacitance and load.
______________________________________________________________________________________
11
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