参数资料
型号: MAX5952CEAX+T
厂商: Maxim Integrated
文件页数: 15/50页
文件大小: 1006K
描述: IC PSE CTRLR FOR POE 36-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1,000
类型: 以太网供电控制器(PoE)
应用: 远程外设(工业控制,相机,数据访问)
内部开关:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-BSOP(0.295",7.50mm 宽)
供应商设备封装: 36-SSOP
包装: 带卷 (TR)
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
______________________________________________________________________________________   15
Detailed Description
The MAX5952 is a quad -48V power controller
designed for use in IEEE 802.3af-compliant/pre-IEEE
802.3at-compatible PSE. This device provides PD dis-
covery, classification, current limit, DC and AC load
disconnect detections in compliance with the IEEE
802.3af standard. The MAX5952 is pin compatible with
the MAX5945/LTC4258/LTC4259A PSE controllers and
provides additional features.
The MAX5952 features a high-power mode which pro-
vides up to 45W per port. The device allows the user to
program the current-limit and overcurrent thresholds up
to 2.5 times the default thresholds. The MAX5952 can
also be programmed to decrease the current-limit and
overcurrent threshold by 15% for high operating voltage
conditions to keep the output power constant.
The MAX5952 provides instantaneous readout of each
port current through the I
2
C interface. The MAX5952 also
provides high-capacitance detection for legacy PDs.
The MAX5952 is fully software configurable and pro-
grammable through an I
2
C-compatible, 3-wire serial
interface with 49 registers. The class-overcurrent
detection function enables system power management
to detect if a PD draws more than the allowable current.
The MAX5952s extensive programmability enhances
system flexibility, enables field diagnosis, and allows
for uses in other applications.
The MAX5952 provides four operating modes to suit
different system requirements. Auto mode allows the
device to operate automatically without any software
supervision. Semi-auto mode automatically detects and
classifies a device connected to a port after initial soft-
ware activation but does not power up that port until
instructed to by software. Manual mode allows total
software control of the device and is useful for system
diagnostics. Shutdown mode terminates all activities
and securely turns off power to the ports.
The MAX5952 provides input undervoltage lockout, input
undervoltage detection, input overvoltage lockout,
overtemperature detection, output voltage slew-rate limit
during startup, power-good, and fault status. The
MAX5952s programmability includes startup timeout,
overcurrent timeout, and load-disconnect detection time-
out.
The MAX5952 communicates with the system micro-
controller through an I
2
C-compatible interface. The
MAX5952 features separate input and output data lines
(SDAIN and SDAOUT) for use with optocoupler isola-
tion. As a slave device, the MAX5952 includes four
address inputs allowing 16 unique addresses. A sepa-
rate INT output and four independent shutdown inputs
(SHD_) provide fast response from a fault to port shut-
down between the MAX5952 and the microcontroller. A
RESET input allows hardware reset of the device.
Reset
Reset is a condition the MAX5952 enters after any of
the following conditions:
1)  After power-up (V
EE
and V
DD
rise above their
UVLO thresholds).
2)  Hardware reset. The RESET input is driven low and
back high again any time after power-up.
3)  Software reset. Writing a 1 into R1Ah[4] any time
after power-up.
4)  Thermal shutdown.
During a reset, the MAX5952 resets its register map to
the reset state as shown in Table 37 and latches in the
state of AUTO (pin 35) and MIDSPAN (pin 2). During
normal operation, change at the AUTO and MIDSPAN
input is ignored. While the condition that caused the
reset persists (i.e. high temperature, RESET input low,
or UVLO conditions) the MAX5952 does not acknowl-
edge any addressing from the serial interface.
Port Reset (R1Ah[3:0])
Set high anytime during normal operation to turn off
power and clear the events and status registers of the
corresponding port. Port reset only resets the events
and status registers.
Midspan Mode
In midspan mode, the device adopts cadence timing
during the detection phase. When cadence timing is
enabled and a failed detection occurs, the port waits
between 2s and 2.4s before attempting to detect again.
Midspan mode is activated by setting R11[1] high. The
status of the MIDSPAN pin is written to R11[1] during
power-up or after a reset. MIDSPAN is internally pulled
low by a 50k?resistor.
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