参数资料
型号: MAX5957AETN+T
厂商: Maxim Integrated
文件页数: 12/25页
文件大小: 634K
描述: IC TRPL PCI EXP/HOT-PLUG 56-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 热交换控制器
应用: 通用型,PCI Express?
内部开关:
电源电压: 3.3V,12V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 56-WFQFN 裸露焊盘
供应商设备封装: 56-TQFN-EP(7x7)
包装: 带卷 (TR)
Triple PCI Express, Hot-Plug Controllers
12   ______________________________________________________________________________________
Pin Description (continued)
PIN
NAME
FUNCTION
22
3.3AUXOC    Slot C 3.3V Auxiliary Power-Supply Output
23, 48, 49
3.3VAUXIN
3.3V Auxiliary Supply Input. 3.3VAUXIN is the input to a charge pump that drives the internal
MOSFETs connecting 3.3VAUXIN to 3.3AUXO_. V
3.3AUXIN
is also used to power the internal control
logic and analog references of the MAX5957/MAX5958 and must always be connected to a supply
between 3V and 3.6V. Bypass 3.3AUXIN with a 0.1礔 capacitor to GND.
24, 46
PGND
Power Ground. Connect externally to GND.
25
TIM
Overcurrent Timeout Programming Input. Connect a resistor between 500& and 500k& from TIM to
GND to program t
FAULT
. Leave TIM unconnected for a default timeout of 11ms.
26
PORADJ
Power-On-Reset Programming Input. Connect a resistor between 500& and 500k& from PORADJ to
GND to program the POR timing. Leave unconnected for a default value of 160ms. Connect
PORADJ to GND to completely skip the POR time delay for PWGD_. Connect PORADJ to GND to
completely skip the POR time delay for PWRGD_ assertion.
27
GND
Ground
28
12VIN
12V Supply Input. V
12VIN
 drives the gates of the MOSFETs connected to 3.3G_. 12VIN powers an
internal charge pump that drives the gates of the MOSFETs connected to 12G_. Bypass 12VIN with
a 1礔 capacitor to GND.
29
N.C.
No Connection. Not internally connected.
30
PRES-DETB
Slot B Present-Detect Input. PRES-DETB accepts inputs from PRSNT#_# on a PCIe connector.
PRES-DETB has an internal 50k& pullup to 3.3VAUXIN. When PRES-DETB is low, the outputs follow
the command from ONB and AUXONB after a 4ms debounced time. When PRES-DETB goes from
low to high, all outputs of the respective slot shut down with no delay.
31
FONB
Slot B Forced-On Input. FONB has a 50k& internal pullup to 3.3VAUXIN. A logic-low on FONB turns
on all slot B outputs as long as the power inputs are within their operating range, regardless of the
status of the other input signals. Leave FONB unconnected for normal operation.
32
PRES-DETA
Slot A Present-Detect Input. PRES-DETA accepts inputs from PRSNT#_# on a PCIe connector.
PRES-DETA has an internal 50k& pullup to 3.3VAUXIN. When PRES-DETA is low, the outputs follow
the command from ONA and AUXONA after a 4ms debounced time. When PRES-DETA goes from
low to high, all outputs of the respective slot shut down with no delay.
33
FONA
Slot A Forced-On Input. FONA has a 50k& internal pullup to 3.3VAUXIN. A logic-low on FONA turns
on all slot A outputs as long as the power inputs are within their operating range, regardless of the
status of the other input signals. Leave FONA unconnected for normal operation.
34
OUTPUT3    Digital Output 3. 4ms debounced digital output of INPUT3.
35
INPUT3
Digital Logic Gate Input 3
36
ONA
Slot A 12V and 3.3V Outputs Enable. A logic-high at ONA turns on the 12V and 3.3V outputs of slot
A (see Table 2).
37
AUXONA
Slot A 3.3V Auxiliary Output Enable. A logic-high at AUXONA turns on the slot A auxiliary output.
38
12SA+
Slot A 12V Positive Current-Sense Input. Connect the positive terminal of the current-sense resistor
to 12SA+ using the Kelvin-sensing technique to ensure accurate current sensing.
39
12SA-
Slot A 12V Negative Current-Sense Input. Connect 12SA- to the negative side of the current-sense
resistor using the Kelvin-sensing technique to ensure accurate current sensing.
40
12GA
Slot A 12V Gate-Drive Output. Connect 12GA to the gate of slot As 12V MOSFET. At power-up,
V
12GA
 is raised to the internal charge-pump voltage level by a constant current.
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