参数资料
型号: MAX5974CETE+
厂商: Maxim Integrated Products
文件页数: 20/27页
文件大小: 0K
描述: IC REG CTRLR FLYBACK PWM 16-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
PWM 型: 电流模式
输出数: 1
频率 - 最大: 600kHz
占空比: 82%
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-WFQFN 裸露焊盘
包装: 管件
MAX5974A/MAX5974B/MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
10 × I LOAD(LIGHT) × R CS
R FFB =
D MAX =
× SYNC
D =
2.43V f SW
When V CSAVG falls below V FFB , the device folds back
the switching frequency to 1/2 the original value to
reduce switching losses and increase the converter effi-
ciency. Calculate the value of R FFB as follows:
I FFB
where R FFB is the resistor between FFB and GND,
I LOAD(LIGHT) is the current at light-load conditions that
triggers frequency foldback, R CS is the value of the
sense resistor connected between CS and PGND, and
I FFB is the current sourced from FFB to R FFB (30 F A typ).
Duty-Cycle Clamping
The maximum duty cycle is determined by the lowest
of three voltages: 2V, the voltage at SS (V SS ), and the
voltage (2.43V - V DCLMP ). The maximum duty cycle is
calculated as:
V MIN
2.43V
where V MIN = minimum (2V, V SS , 2.43V - V DCLMP ).
SS
By connecting a resistor between SS and ground, the
voltage at SS can be made to be lower than 2V. V SS is
calculated as follows:
V SS
= R SS × I SS-CH
where R SS is the resistor connected between SS and
GND, and I SS-CH is the current sourced from SS to R SS
(10 F A typ).
DCLMP
Oscillator Synchronization
The internal oscillator can be synchronized to an external
clock by applying the clock to DITHER/SYNC directly. The
external clock frequency can be set anywhere between
1.1x to 2x the internal clock frequency.
Using an external clock increases the maximum duty
cycle by a factor equal to f SYNC /f SW . This factor should
be accounted for in setting the maximum duty cycle
using any of the methods described in the Duty-Cycle
Clamping section. The formula below shows how the
maximum duty cycle is affected by the external clock
frequency:
V MIN f
MAX
where V MIN is described in the Duty-Cycle Clamping
section, f SW is the switching frequency as set by the
resistor connected between RT and GND, and f SYNC is
the external clock frequency.
Frequency Dithering for Spread-
Spectrum Applications (Low EMI)
The switching frequency of the converter can be dith-
ered in a range of Q 10% by connecting a capaci-
tor from DITHER/SYNC to GND, and a resistor from
DITHER/SYNC to RT as shown in the Typical Application
Circuits . This results in lower EMI.
A current source at DITHER/SYNC charges the capaci-
tor C DITHER to 2V at 50 F A. Upon reaching this trip point,
it discharges C DITHER to 0.4V at 50 F A. The charging
and discharging of the capacitor generates a triangular
waveform on DITHER/SYNC with peak levels at 0.4V and
2V and a frequency that is equal to:
To set D MAX using supply voltage feed-forward, connect
a resistive divider between the supply voltage, DCLMP,
and GND as shown in the Typical Application Circuits.
This feed-forward duty-cycle clamp ensures that the
f TRI =
50 μ A
C DITHER × 3.2V
R DCLMP2
4 R RT
external n-channel MOSFET is not stressed during sup-
ply transients. V DCLMP is calculated as follows:
V DCLMP
= × V S
R DCLMP1 + R DCLMP2
where R DCLMP1 and R DCLMP2 are the resistive divider
values shown in the Typical Application Circuits and V S
is the input supply voltage.
20
Typically, f TRI should be set close to 1kHz. The resistor
R DITHER connected from DITHER/SYNC to RT deter-
mines the amount of dither as follows:
=
%DITHER ×
3 R DITHER
where %DITHER is the amount of dither expressed as a
percentage of the switching frequency. Setting R DITHER
to 10 x R RT generates Q 10% dither.
Maxim Integrated
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