参数资料
型号: MAX6324HUT46-T
厂商: Maxim Integrated Products
文件页数: 10/13页
文件大小: 0K
描述: IC MPU/WATCHDG 719-1.3MS SOT23-6
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 100 ms
电压 - 阀值: 4.63V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SOT-23-6
供应商设备封装: SOT-6
包装: 带卷 (TR)
μP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
WDPO to MR Loopback
START
SET WDI
LOW
SUBROUTINE OR
PROGRAM LOOP
SET WDI HIGH
RETURN
END
Figure 9. Watchdog Flow Diagram
V CC
500pF
V CC
An error detected by the watchdog often indicates that
a problem has occurred in the μP code execution. This
could be a stalled instruction or a loop from which the
processor cannot free itself. If the μP will still respond
to a nonmaskable input (NMI), the processor can be
redirected to the proper code sequence by connecting
the WDPO output to an NMI input. Internal RAM data
should not be lost, but it may have been contaminated
by the same error that caused the watchdog to time
out.
If the processor will not recognize NMI inputs, or if the
internal data is considered potentially corrupted when
a watchdog error occurs, the processor should be
restarted with a reset function. To obtain proper reset
timing characteristics, the WDPO output should be
connected to the MR input, and the RESET output
should drive the μP RESET input (Figure 10). The short
1ms WDPO pulse output will assert the manual reset
input and force the RESET output to assert for the full
reset timeout period (100ms min). All internal RAM data
is lost during the reset period, but the processor is
guaranteed to begin in the proper operating state.
V CC
MR
*MAX6324 ONLY
Figure 10. WDPO to MR Loopback Circuit
MAX6323
MAX6324
GND
RESET
WDI
WDPO
*R PULLUP
RESET
I/O
μ P
10
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