参数资料
型号: MAX6365LKA44+T
厂商: Maxim Integrated Products
文件页数: 9/15页
文件大小: 0K
描述: IC SUPERVISOR MPU LP SOT23-8
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 备用电池电路
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 150 ms
电压 - 阀值: 4.38V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-8
供应商设备封装: SOT-23-8
包装: 带卷 (TR)
SOT23, Low-Power μP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
OUT goes high and stays high regardless of any sub-
sequent transitions on CE IN during the reset event.
When CE OUT is disconnected from CE IN, CE OUT is
Table 1. Input and Output Status in
Battery-Backup Mode
actively pulled up to OUT.
The propagation delay through the chip-enable circuit-
ry depends on both the source impedance of the drive
to CE IN and the capacitive loading at CE OUT. The
chip-enable propagation delay is production tested
from the 50% point of CE IN to the 50% point of CE
OUT, using a 50 ? driver and 50pF load capacitance.
Minimize the capacitive load at CE OUT to minimize
propagation delay, and use a low-output-impedance
driver.
Backup-Battery Switchover
In a brownout or power failure, it may be necessary to
preserve the contents of the RAM. With a backup bat-
tery installed at BATT, the MAX6365–MAX6368 auto-
PIN
V CC
OUT
BATT
RESET/ RESET
BATT ON
MR , RESET IN,
CE IN, WDI
CE OUT
STATUS
Disconnected from OUT
Connected to BATT
Connected to OUT. Current drawn from
the battery is less than 1 μ A (at V BATT =
2.8V, excluding I OUT ) when V CC = 0V.
Asserted
High state
Inputs ignored
Connected to OUT
matically switch the RAM to backup power when V CC
falls. The MAX6367 has a BATT ON output that goes
high in battery-backup mode. These devices require
two conditions before switching to battery-backup
mode:
1) V CC must be below the reset threshold.
2) V CC must be below V BATT .
Table 1 lists the status of the inputs and outputs in bat-
tery-backup mode. The devices do not power up if the
only voltage source is on BATT. OUT only powers up
from V CC at startup.
Manual Reset Input (MAX6365 Only)
Many μP-based products require manual reset capabili-
ty, allowing the user or external logic circuitry to initiate a
reset. For the MAX6365, a logic low on MR asserts reset.
Reset remains asserted while MR is low and for a mini-
mum of 150ms (t RP ) after it returns high. MR has an inter-
nal 20k ? pullup resistor to V CC . This input can be driven
with TTL/CMOS logic levels or with open-drain/collector
outputs. Connect a normally open momentary switch
from MR to GND to create a manual reset function; exter-
nal debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environ-
ment, connect a 0.1μF capacitor from MR to GND to pro-
vide additional noise immunity.
V CC OR BATT
RESET
THRESHOLD V TH
CE IN
CE OUT
RESET-TO-CE OUT DELAY (12 μ s)
t RD
t RD
*
RESET
t RP
t RP
RESET
* IF CE IN GOES HIGH BEFORE RESET ASSERTS,
CE OUT GOES HIGH WITHOUT DELAY AS
CE IN GOES HIGH.
Figure 1. Reset and Chip-Enable Timing
_______________________________________________________________________________________
9
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