参数资料
型号: MAX6366PKA31+T
厂商: Maxim Integrated Products
文件页数: 8/15页
文件大小: 0K
描述: IC SUPERVISOR MPU LP SOT23-8
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
类型: 备用电池电路
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 150 ms
电压 - 阀值: 3.08V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-8
供应商设备封装: SOT-23-8
包装: 标准包装
其它名称: MAX6366PKA31+TDKR
SOT23, Low-Power μP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
Functional Diagram
BATT ON (MAX6367 ONLY)
1.235V
MAX6365
V CC
MAX6366
MAX6367
MAX6368
OUT
CHIP-ENABLE
OUTPUT
CONTROL
BATT
CE IN
CE OUT
MR
(MAX6365 ONLY)
WDI
(MAX6366 ONLY)
RESET IN
20k
WATCHDOG
TRANSITION
DETECTOR
RESET
GENERATOR
WATCHDOG
TIMER
RESET
(RESET)
(MAX6368 ONLY)
1.235V
GND
Detailed Description
The Typical Operating Circuit shows a typical connec-
tion for the MAX6365–MAX6368. OUT powers the static
random-access memory (SRAM). If V CC is greater than
the reset threshold (V TH ), or if V CC is lower than V TH
but higher than V BATT , V CC is connected to OUT. If
V CC is lower than V TH and V CC is less than V BATT ,
BATT is connected to OUT. OUT supplies up to 150mA
from V CC . In battery-backup mode, an internal MOSFET
connects the backup battery to OUT. The on-resistance
of the MOSFET is a function of backup-battery voltage
and is shown in the BATT-to-OUT On-Resistance vs.
Temperature graph in the Typical Operating Char-
acteristics.
Chip-Enable Signal Gating
The MAX6365–MAX6368 provide internal gating of CE
signals to prevent erroneous data from being written to
CMOS RAM in the event of a power failure. During nor-
mal operation, the CE gate is enabled and passes all
CE transitions. When reset asserts, this path becomes
disabled, preventing erroneous data from corrupting
the CMOS RAM. All of these devices use a series trans-
mission gate from CE IN to CE OUT. The 2ns propaga-
tion delay from CE IN to CE OUT allows the devices to
be used with most μPs and high-speed DSPs.
During normal operation, CE IN is connected to CE
OUT through a low on-resistance transmission gate.
This is valid when reset is not asserted. If CE IN is high
when reset is asserted, CE OUT remains high regard-
less of any subsequent transitions on CE IN during the
reset event.
If CE IN is low when reset is asserted, CE OUT is held
low for 12μs to allow completion of the read/write oper-
ation (Figure 1). After the 12μs delay expires, the CE
8
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