参数资料
型号: MAX6391KA23+T
厂商: Maxim Integrated Products
文件页数: 5/9页
文件大小: 0K
描述: IC SUPERVISOR MPU DL SOT23-8
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 多压监控器
监视电压数目: 2
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 140 ms/可调最小值
电压 - 阀值: 2.32V,可调
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-8
供应商设备封装: SOT-23-8
包装: 带卷 (TR)
Dual-Voltage μP Supervisory Circuits
with Sequenced Reset Outputs
Pin Description
MAX6391
PIN
MAX6392
NAME
FUNCTION
Input Voltage for RESET2 Monitor. High-impedance input for internal reset
1
1
RESET IN2
comparator. Connect this pin to an external resistive-divider network to set the reset
threshold voltage.
2
2
V CC
Supply Voltage and Input Voltage for Primary Supply Monitor
RESET2 Delay Set Capacitor. Connect to V CC for a fixed 140ms (min) timeout period
3
3
CSRT
or to an external capacitor for a user-adjustable timeout period after V CC exceeds its
minimum threshold.
4
4
GND
Ground
Secondary Reset Output, Open-Drain, Active-Low. RESET2 changes from high to low
5
5
RESET2
when either V CC or RESET IN2 drop below their thresholds. RESET2 remains low for a
user-adjustable timeout period (see CSRT) or a fixed 140ms (min) after V CC and
RESET IN2 meet their minimum thresholds.
6
6
R2
47k ? Internal Pullup Resistor for RESET2 . Connect to external voltage for RESET2
high pullup.
Primary Reset Output, Open-Drain (MAX6391) or Push-Pull (MAX6392), Active-Low.
7
7
RESET1
RESET1 changes from HIGH to LOW when the V CC input drops below the selected
reset threshold. RESET1 remains LOW for the reset timeout period after V CC exceeds
the minimum threshold.
8
R1
47k ? Internal Pullup Resistor for RESET1 . Connect to external voltage for RESET1
high pullup.
Manual Reset, Active-Low, Internal 47k ? Pullup to V CC . Pull LOW to force a reset.
8
MR
RESET1 and RESET2 remain asserted as long as MR is LOW and for the RESET1 and
RESET2 timeout periods after MR goes HIGH. Leave unconnected or connect to V CC
if unused.
Detailed Description
Each device includes a pair of voltage monitors with
sequenced reset outputs. The first block monitors V CC
only ( RESET1 output is independent of the RESET IN2
monitor). It asserts a reset signal (LOW) whenever V CC
is below the preset voltage threshold. RESET1 remains
asserted for at least 140ms after V CC rises above the
reset threshold. RESET1 timing is internally set in each
device. V CC voltage thresholds are available from
1.57V to 4.63V. In all cases V CC acts as the master
supply (all resets are asserted when V CC goes below
its selected threshold). The V CC input also acts as the
device power supply.
The second block monitors both RESET IN2 and V CC . It
asserts a reset signal (LOW) whenever RESET IN2 is
below the 625mV threshold or V CC is below its reset
threshold. RESET2 remains asserted for a fixed 140ms
(min) or a user-adjustable time period after RESET IN2
rises above the 625mV reset threshold and RESET1 is
deasserted. Resets are guaranteed valid for V CC down
to 1V.
The timing diagram in Figure 2 shows the reset timing
characteristics of the MAX6391/MAX6392. As shown in
Figure 2, RESET1 deasserts 140ms (min) (t RP1 ) after
V CC exceeds the reset threshold. RESET2 deasserts
t RP2 (140ms minimum or a user-adjustable timeout peri-
od) after RESET IN2 exceeds 625mV and RESET1 is
deasserted. When RESET IN2 drops below 625mV
while V CC is above the reset threshold, RESET2 asserts
within 10μs typ. RESET1 is unaffected when this hap-
pens. When V CC falls below V TH1 , RESET2 always
asserts before RESET1 (t RD2 < t RD1 ).
_______________________________________________________________________________________
5
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