参数资料
型号: MAX6419UK35+T
厂商: Maxim Integrated Products
文件页数: 7/12页
文件大小: 0K
描述: IC RESET MPU LOW PWR SOT23-5
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 多压监控器
监视电压数目: 2
输出: 推挽式,图腾柱
复位: 高有效
复位超时: 可调节/可选择
电压 - 阀值: 3.5V,可调
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SC-74A,SOT-753
供应商设备封装: SOT-23-5
包装: 带卷 (TR)
MAX6412–MAX6420
Low-Power, Single/Dual-Voltage μP Reset Circuits
with Capacitor-Adjustable Reset Timeout Delay
V MON_TH
V CC
V CC
MAX6420
ONLY
R1
1.26V
LASER-TRIMMED
RESISTORS
RESET
CIRCUITRY
(RESET)
RESET
R L
μ P
R2
RESET IN
GND
SRT
MAX6418
MAX6419
MAX6420
C SRT
Figure 4. MAX6418/MAX6419/MAX6420 Monitoring Two Voltages
Dual-Voltage Monitoring
(MAX6418/MAX6419/MAX6420)
The MAX6418/MAX6419/MAX6420 contain both facto-
ry-trimmed threshold voltages and an adjustable reset
threshold input, allowing the monitoring of two voltages,
V CC and V MON_TH (see Figure 4). Reset is asserted
when either of the voltages falls below its respective
threshold voltage.
Application Information
Selecting a Reset Capacitor
The reset timeout period is adjustable to accommodate
a variety of μP applications. Adjust the reset timeout
period (t RP ) by connecting a capacitor (C SRT ) between
SRT and ground. Calculate the reset timeout capacitor
as follows:
C SRT = (t RP - 275μs) / (2.71   10 6 )
where t RP is in seconds and C SRT is in Farads
Maxim Integrated
The reset delay time is set by a current/capacitor-con-
trolled ramp compared to an internal 0.65V reference.
An internal 240nA ramp current source charges the
external capacitor. The charge to the capacitor is
cleared when a reset condition is detected. Once the
reset condition is removed, the voltage on the capacitor
ramps according to the formula: dV/dt = I/C. The C SRT
capacitor must ramp to 0.65V to deassert the reset.
C SRT must be a low-leakage (<10nA) type capacitor,
ceramic is recommended.
Operating as a Voltage Detector
The MAX6412–MAX6420 can be operated in a voltage
detector mode by leaving SRT unconnected. The reset
delay times for V CC rising above or falling below the
threshold are not significantly different. The reset output
is deasserted smoothly without false pulses.
7
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