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参数资料
| 型号： | MAX6426UK50+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 6/10页 |
| 文件大小： | 0K |
| 描述： | IC MPU/RESET CIRC 5.00V SOT23-5 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 5V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SC-74A，SOT-753 |
| 供应商设备封装： | SOT-23-5 |
| 包装： | 带卷 (TR) |
Low-Power, SC70/SOT μP Reset Circuits with
Capacitor-Adjustable Reset Timeout Delay
V CC
Table 1. Reset Threshold Voltage Suffix
SUFFIX
16
MIN
1.536
TYP
1.575
MAX
1.614
MAX6421
MAX6424
V CC
RESET
17
18
19
20
21
1.623
1.755
1.853
1.950
2.048
1.665
1.800
1.900
2.000
2.100
1.707
1.845
1.948
2.050
2.153
GND
Figure 3. Ensuring RESET Valid to V CC = 0
V CC
V CC
MAX6422
RESET
GND
100k ?
100k ?
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
2.133
2.313
2.340
2.438
2.559
2.633
2.730
2.852
2.925
2.998
3.120
3.218
3.315
3.413
3.510
3.608
3.705
3.803
3.900
2.188
2.313
2.400
2.500
2.625
2.700
2.800
2.925
3.000
3.075
3.200
3.300
3.400
3.500
3.600
3.700
3.800
3.900
4.000
2.243
2.371
2.460
2.563
2.691
2.768
2.870
2.998
3.075
3.152
3.280
3.383
3.485
3.558
3.690
3.793
3.895
3.998
4.100
Figure 4. Ensuring RESET Valid to V CC = 0
tor between RESET and V CC holds RESET high when
V CC falls below 1V (Figure 4). Open-drain RESET ver-
sions are not recommended for applications requiring
valid logic for V CC down to zero.
Layout Consideration
SRT is a precise current source. When developing the
layout for the application, be careful to minimize board
capacitance and leakage currents around this pin.
Traces connected to SRT should be kept as short as
possible. Traces carrying high-speed digital signals
41
42
43
44
45
46
47
48
49
50
3.998
4.095
4.193
4.266
4.388
4.509
4.583
4.680
4.778
4.875
4.100
4.200
4.300
4.375
4.500
4.625
4.700
4.800
4.900
5.000
4.203
4.305
4.408
4.484
4.613
4.741
4.818
4.920
5.023
5.125
and traces with large voltage potentials should be rout-
ed as far from SRT as possible. Leakage current and
stray capacitance (e.g., a scope probe) at this pin
could cause errors in the reset timeout period. When
evaluating these parts, use clean prototype boards to
ensure accurate reset periods.
6
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