参数资料
型号: MAX6454UT22S-T
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 电源管理
英文描述: µP Supervisors with Separate VCC Reset and Manual Reset Outputs
中文描述: 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6
封装: SOT-23, 6 PIN
文件页数: 8/10页
文件大小: 189K
代理商: MAX6454UT22S-T
MAX6453–MAX6456
P Supervisors with Separate VCC Reset and
Manual Reset Outputs
_______________________________________________________________________________________
7
Applications Information
Interrupt Before Reset
To minimize data loss and speed system recovery/test,
many applications interrupt the processor or reset only
portions of the system before a processor hard reset is
asserted. The extended setup time of the MAX6455/
MAX6456
MR input allows the same pushbutton (Figure
4) to control both the interrupt and hard reset functions.
If the pushbutton is closed for less than 3.36s (typ), the
processor is only interrupted (
MROUT). If the system
still does not respond properly, the pushbutton can be
closed for the full extended setup period (3.36s typ) to
hard reset the processor (
RESET). If desired, connect a
LED to the
RESET output to turn off (or on) to signify
when the pushbutton is closed long enough for a hard
reset (the same LED can be used as the front panel
power-on display).
Interfacing to Other Voltages
for Logic Compatibility
The open-drain
RESET output can be used to interface
to a P with other logic levels. As shown in Figure 5, the
open-drain output can be connected to voltages from 0
to 6V.
Generally, the pullup resistor connected to the
RESET
connects to the supply voltage being monitored at the
IC’s VCC pin. However, some systems might use the
open-drain output to level-shift from the monitored sup-
ply to reset circuitry powered by some other supply
(Figure 5). Keep in mind that as the supervisor’s VCC
decreases toward 1V, so does the IC’s ability to sink
current at
RESET (RESET is pulled high as VCC decays
toward 0). The voltage where this occurs depends on
the pullup resistor value and the voltage to which it is
connected.
Ensuring a Valid
RESET Down to VCC = 0V
(Push-Pull
RESET)
When VCC falls below 1V, RESET current-sinking capa-
bilities decline drastically. The high-impedance CMOS-
logic inputs connected to
RESET can drift to
undetermined voltages. This presents no problem in
most applications, because most Ps and other circuit-
ry do not operate with VCC below 1V.
In applications where
RESET must be valid down to 0V,
add a pulldown resistor between
RESET and GND for
the push/pull outputs. The resistor sinks any stray leak-
age currents, holding
RESET low (Figure 6). The value
of the pulldown resistor is not critical; 100k
is large
enough not to load
RESET and small enough to pull
RESET to ground. The external pulldown cannot be
used with the open-drain reset outputs.
Transient Immunity
In addition to issuing a reset to the P during power-up,
power-down and brownout conditions, these supervisors
are relatively immune to short duration falling transients
(glitches). The graph Maximum Transient Duration vs.
Reset Threshold Overdrive in the Typical Operating
Characteristics section shows this relationship.
The area below the curves of the graph is the region in
which these devices typically do not generate a reset
pulse. This graph was generated using a negative
going pulse applied to VCC, starting above the actual
reset threshold (VTH) and ending below it by the magni-
tude indicated (reset-threshold overdrive). As the mag-
nitude of the transient increases (VCC goes further
below the reset threshold), the maximum allowable
pulse width decreases. Typically, a VCC transient that
goes 100mV below the reset threshold and lasts 20s
or less does not cause a reset pulse to be issued.
MAX6453
MAX6455
RSTIN
VCC
R1
R2
RESET
GND
VMON_TH = 0.63 x (R1 + R2) / R2
VMON_TH
VCC
Figure 3. Calculating The Monitored Threshold Voltages
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