参数资料
型号: MAX6456UT31S+T
厂商: Maxim Integrated Products
文件页数: 7/11页
文件大小: 0K
描述: IC MPU SUPER 3.075V SOT23-6
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 多压监控器
监视电压数目: 2
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 3.075V,可调
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-6
供应商设备封装: SOT-6
包装: 带卷 (TR)
μP Supervisors with Separate V CC Reset and
Manual Reset Outputs
Generally, the pullup resistor connected to the RESET
V MON_TH
V CC
connects to the supply voltage being monitored at the
IC’s V CC pin. However, some systems might use the
open-drain output to level-shift from the monitored sup-
ply to reset circuitry powered by some other supply
R1
RSTIN
MAX6453
MAX6455
V CC
(Figure 5). Keep in mind that as the supervisor’s V CC
decreases toward 1V, so does the IC’s ability to sink
current at RESET ( RESET is pulled high as V CC decays
toward 0). The voltage where this occurs depends on
the pullup resistor value and the voltage to which it is
R2
connected.
GND
V MON_TH = 0.63 x (R1 + R2) / R2
RESET
Ensuring a Valid RESET Down to V CC = 0V
(Push-Pull RESET )
When V CC falls below 1V, RESET current-sinking capa-
bilities decline drastically. The high-impedance CMOS-
logic inputs connected to RESET can drift to
undetermined voltages. This presents no problem in
most applications, because most μPs and other circuit-
ry do not operate with V CC below 1V.
Figure 3. Calculating The Monitored Threshold Voltages
Applications Information
Interrupt Before Reset
To minimize data loss and speed system recovery/test,
many applications interrupt the processor or reset only
portions of the system before a processor hard reset is
asserted. The extended setup time of the MAX6455/
MAX6456 MR input allows the same pushbutton (Figure
4) to control both the interrupt and hard reset functions.
If the pushbutton is closed for less than the extended
setup timeout period, the processor is only interrupted
( MROUT ). If the system still does not respond properly,
the pushbutton can be closed for the full extended
setup timeout period to hard reset the processor
( RESET ). If desired, connect a LED to the RESET output
to turn off (or on) to signify when the pushbutton is
closed long enough for a hard reset (the same LED can
be used as the front panel power-on display).
Interfacing to Other Voltages
for Logic Compatibility
The open-drain RESET output can be used to interface
to a μP with other logic levels. As shown in Figure 5, the
open-drain output can be connected to voltages from 0
to 6V.
In applications where RESET must be valid down to 0V,
add a pulldown resistor between RESET and GND for
the push/pull outputs. The resistor sinks any stray leak-
age currents, holding RESET low (Figure 6). The value
of the pulldown resistor is not critical; 100k Ω is large
enough not to load RESET and small enough to pull
RESET to ground. The external pulldown cannot be
used with the open-drain reset outputs.
Transient Immunity
In addition to issuing a reset to the μP during power-up,
power-down and brownout conditions, these supervisors
are relatively immune to short duration falling transients
(glitches). The graph Maximum Transient Duration vs.
Reset Threshold Overdrive in the Typical Operating
Characteristics section shows this relationship.
The area below the curves of the graph is the region in
which these devices typically do not generate a reset
pulse. This graph was generated using a negative
going pulse applied to V CC , starting above the actual
reset threshold (V TH ) and ending below it by the magni-
tude indicated (reset-threshold overdrive). As the mag-
nitude of the transient increases (V CC goes further
below the reset threshold), the maximum allowable
pulse width decreases. Typically, a V CC transient that
goes 100mV below the reset threshold and lasts 20μs
or less does not cause a reset pulse to be issued.
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7
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