参数资料
型号: MAX6457UKD3B+T
厂商: Maxim Integrated Products
文件页数: 9/15页
文件大小: 0K
描述: IC SUPPLY VOLT MONITOR SOT23-5
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 90 ms
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SC-74A,SOT-753
供应商设备封装: SOT-23-5
包装: 标准包装
产品目录页面: 1417 (CN2011-ZH PDF)
其它名称: MAX6457UKD3B+TDKR
MAX6457–MAX6460
High-Voltage, Low-Current Voltage Monitors in
SOT Packages
>V TH+
IN+
<V TH-
V CC
CLEAR
0
V CC
OUT
t TP
t TP
t TP
0
Figure 7. Timing Diagram (MAX6457)
Hysteresis
Hysteresis adds noise immunity to the voltage monitors
BATTERY
+21V
IN
DC-DC
OUT
and prevents oscillation due to repeated triggering
when V IN is near the threshold trip voltage. The hystere-
sis in a comparator creates two trip points: one for the
rising input voltage (V TH +) and one for the falling input
CHARGER
V CC
CONVERTER
SHDN
voltage (V TH -). These thresholds are shown in Figure 6.
The internal hysteresis options of the MAX6457/
MAX6458/MAX6459 are designed to eliminate the need
for adding an external hysteresis circuit.
5-CELL
Li+
BATTERY
STACK
R1
R2
IN+
MAX6457–
MAX6460
OUT
(OUTA FOR
MAX6459)
R PULLUP
LOAD
Timeout Period
The timeout period (t TP ) for the MAX6457 is the time
from when the input (IN+) crosses the rising input
threshold (V TH +) to when the output goes high (see
Figures 6 and 7). For the MAX6458, the monitored volt-
age must be in the “window” before the timeout starts.
The MAX6459 and MAX6460 do not offer the extended
timeout option (150ms). The extended timeout period is
suitable for overvoltage protection applications requir-
ing transient immunity to avoid false output assertion
due to noise spikes.
Latched-Output Operation
The MAX6457 features a digital latch input ( CLEAR ) to
latch any overvoltage event. If the voltage on IN+ (V IN +)
is below the internal threshold (V TH -), or if V CC is below
Maxim Integrated
GND
Figure 8. Undervoltage Lockout Typical Application Circuit
4V, OUT remains low regardless of the state of CLEAR .
Drive CLEAR high to latch OUT high when V IN + exceeds
V TH +. When CLEAR is high, OUT does not deassert if
V IN + drops back below V IN -. Toggle CLEAR to deassert
OUT. Drive CLEAR low to make the latch transparent
(Figure 7). CLEAR must be low when powering up the
MAX6457. To initiate self-clear at power-up, add a 100k ?
pullup resistor from CLEAR to V CC and a 1μF capacitor
from CLEAR to GND to hold CLEAR low. Connect
CLEAR to GND when not used. See Figure 9.
9
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