参数资料
型号: MAX6470TA25BD3+T
厂商: Maxim Integrated
文件页数: 12/20页
文件大小: 0K
描述: IC REG LDO 2.5V/ADJ .3A 8-TDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
稳压器拓扑结构: 正,固定式或可调式
输出电压: 2.5V,1.25 V ~ 5.5 V
输入电压: 2.5 V ~ 5.5 V
电压 - 压降(标准): 0.158V @ 300mA,-
稳压器数量: 1
电流 - 输出: 300mA(最小)
电流 - 限制(最小): 450mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-WDFN 裸露焊盘
供应商设备封装: 8-TDFN-EP(3x3)
包装: 带卷 (TR)
300mA LDO Linear Regulators with Internal
Microprocessor Reset Circuit
Power Dissipation Consideration
For the SOT23 package, any pin except the SET pin
can be used as a heatsink. If the SET pin is used as a
heatsink, excessive parasitic capacitance can affect
stability. For the TDFN package, the exposed metal
pad on the back side of a package connects to GND of
the chip. This metal pad can be used as a heatsink.
UCSP Consideration
For general UCSP package information and PC layout
considerations, refer to Maxim Application Note: Wafer-
Level Chip-Scale Package.
Table 1. Output Voltage Suffix Guide
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that might not perform equally to
a packaged product through traditional mechanical
reliability tests. CSP reliability is integrally linked to the
user’s assembly methods, circuit-board material, and
usage environment. The user should closely review
these areas when considering a CSP package.
Performance through operating life test and moisture
resistance remains uncompromised, because it is pri-
marily determined by the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a CSP package. CSPs are attached through
direct solder contact to the user’s PC board, forgoing
the inherent stress relief of a packaged product’s lead
frame. Solder-joint contact integrity must be considered.
Information on Maxim’s qualification plan, test data, and
recommendations are detailed in the UCSP application
note on Maxim’s website at www.maxim-ic.com.
Table 2. Reset Threshold Accuracy Guide
SUFFIX
15
16
17
18
OUTPUT
VOLTAGE (V)
1.5
1.6
1.7
1.8
SUFFIX
A
B
V OUT RESET
TOLERANCE (%)
-7.5
-12.5
19
1.9
Table 3. Reset Timeout Delay Guide
20
21
22
23
24
25
26
27
28
285
29
30
31
32
33
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.85
2.9
3.0
3.1
3.2
3.3
SUFFIX
D1
D2
D3
D4
MINIMUM RESET
TIMEOUT PERIOD (ms)
2.5
20
150
1200
Note: Factory-trimmed custom output voltages may be avail-
able; contact factory for availability.
12
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