参数资料
型号: MAX6722UTZGD6
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 电源管理
英文描述: Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits
中文描述: 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封装: MO-178, SOT-23, 8 PIN
文件页数: 19/19页
文件大小: 715K
代理商: MAX6722UTZGD6
Detailed Description
Supply Voltages
The MAX6715–MAX6729 microprocessor (P) supervi-
sory circuits maintain system integrity by alerting the P
to fault conditions. These ICs are optimized for systems
that monitor two or three supply voltages. The output-
reset state is guaranteed to remain valid while either
VCC1 or VCC2 is above 0.8V.
Threshold Levels
Input voltage threshold level combinations are indicat-
ed by a two-letter code in the Reset Voltage Threshold
Suffix Guide (Table 1). Contact factory for availability of
other voltage threshold combinations.
Reset Outputs
The MAX6715–MAX6729 provides an active-low reset
output (RST) and the MAX6725/MAX6726 provides
both an active-high (RST) and an active-low reset out-
put (RST). RST, RST, RST1, and RST2 are asserted
when the voltage at either VCC1 or VCC2 falls below the
voltage threshold level, RSTIN drops below threshold,
or MR is pulled low. Once reset is asserted it stays low
for the reset timeout period (see Table 2). If VCC1,
VCC2, or RSTIN goes below the reset threshold before
the reset timeout period is completed, the internal timer
MAX6715–MAX6729
Dual/Triple Ultra-Low-Voltage SOT23 P
Supervisory Circuits
_______________________________________________________________________________________
9
Pin Description (continued)
PIN
MAX6715/
MAX6716
MAX6717/
MAX6718
MAX6719/
MAX6720
MAX6721/
MAX6722
MAX6723/
MAX6724
MAX6725/
MAX6726
MAX6727
MAX6728/
MAX6729
NAME
FUNCTION
——
———
——
4
PFO
Active-Low Power-Fail
Monitor Output, Open-
Drain or Push-Pull. PFO is
asserted low when PFI is
less than 0.626V. PFO
deasserts without a reset
timeout period. Open-
drain outputs require an
external pullup resistor.
Push-pull outputs are
referenced to VCC1.
——
———
4
RST
Active-High Reset
Output, Open-Drain or
Push-Pull. RST changes
from low to high when
VCC1 or VCC2 drops
below selected reset
thresholds, RSTIN is
below threshold, MR is
pulled low, or the
watchdog triggers a
reset. RST remains HIGH
for the reset timeout
period after VCC1/
VCC 2/RSTIN exceed the
device reset thresholds,
MR goes low to high, or
the watchdog triggers a
reset. Open-drain outputs
require an external pullup
resistor. Push-pull
outputs are referenced to
VCC1.
相关PDF资料
PDF描述
MAX6722UTZWD1 Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits
MAX6722UTZWD2 Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits
MAX6722UTZWD4 Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits
MAX6722UTZWD5 Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits
MAX6723UTLTD1 Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits
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