参数资料
型号: MAX6725KASVD3+T
厂商: Maxim Integrated Products
文件页数: 11/19页
文件大小: 0K
描述: IC SUPERVISOR MPU SOT23-8
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 多压监控器
监视电压数目: 3
输出: 开路漏极,开路漏极
复位: 高有效/低有效
复位超时: 最小为 140 ms
电压 - 阀值: 1.575V,3.075V,可调
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-8
供应商设备封装: SOT-23-8
包装: 带卷 (TR)
Dual/Triple Ultra-Low-Voltage SOT23 μP
Supervisory Circuits
V IN
A
V CC 1 V CC 2
RESET TO OTHER SYSTEM COMPONENTS
MAX6728/
R1
PFI
MAX6729
PFO
V TRIP = V PFI
( R1 R2 + R2 )
MAX6715–
MAX6729
4.7k ?
μ P
R2
V CC 2
RST
RESET
V CC 1
GND
V CC
B
GND
GND
[ (
R1
PFI
MAX6728/
MAX6729
PFO
V TRIP = R2 (V PFI ) 1 + 1
R1 R2
)
-
V CC
R1
]
Figure 4. Interfacing to μPs with Bidirectional Reset I/O
Applications Information
V IN
R2
GND
V PFI = 626.5mV
Interfacing to μPs with Bidirectional
Reset Pins
Most microprocessors with bidirectional reset pins can
interface directly to open-drain RST output options.
Systems simultaneously requiring a push-pull RST out-
Figure 3. Using Power-Fail Input to Monitor an Additional
Power-Supply a) V IN is Positive b) V IN is Negative
providing an early power-fail warning so software can
conduct an orderly system shutdown. It can also be
used to monitor supplies other than V CC 1 or V CC 2 by
setting the power-fail threshold with a resistor-divider, as
shown in Figure 3. PFI is the input to the power-fail com-
parator. The typical comparator delay is 2μs from PFI to
PFO . Connect PFI to ground of V CC 1 if unused.
Ensuring a Valid Reset Output
Down to V CC = 0
The MAX6715–MAX6729 are guaranteed to operate
properly down to V CC = 0.8V. In applications that
require valid reset levels down to V CC = 0 use a pull-
down resistor at RST to ground. The resistor value used
is not critical, but it must be large enough not to load
the reset output when V CC is above the reset threshold.
For most applications, 100k ? is adequate. This config-
uration does not work for the open-drain outputs of the
MAX6715/MAX6717/MAX6719/MAX6721/MAX6723/
MAX6725/MAX6727/MAX6728. For push-pull, active-
high RST output connect the external resistor as a
pullup from RST to V CC 1.
put and a bidirectional reset interface can be in logic
contention. To prevent contention, connect a 4.7k ?
resistor between RST and the μP’s reset I/O port as
shown in Figure 4.
Adding Hysteresis to the Power-Fail
Comparator
The power-fail comparator has a typical input hysteresis
of 3mV. This is sufficient for most applications where a
power-supply line is being monitored through an external
voltage-divider (see the Power-Fail Comparator section).
If additional noise margin is desired, connect a resistor
between PFO and PFI as shown in Figure 5. Select the
values of R1, R2, and R3 so PFI sees V PFI (626mV) when
V EXT falls to its power-fail trip point (V FAIL ) and when VIN
rises to its power-good trip point (V GOOD ). The hysteresis
window extends between the specified V FAIL and V GOOD
thresholds. R3 adds the additional hysteresis by sinking
current from the R1/R2 divider network when PFO is logic
low and sourcing current into the network when PFO is
logic high. R3 is typically an order of magnitude greater
than R1 or R2.
The current through R2 should be at least 2.5μA to
ensure that the 25nA (max) PFI input current does not
significantly shift the trip points. Therefore, R2 <
V PFI /2.5μA < 248k ? for most applications. R3 will provide
additional hysteresis for PFO push-pull (V OH = V CC 1) or
open-drain (V OH = V PULLUP ) applications.
______________________________________________________________________________________
11
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