参数资料
型号: MAX6740XKVFD3+T
厂商: Maxim Integrated Products
文件页数: 8/16页
文件大小: 0K
描述: IC SUPERVISOR MPU LP SC70-5
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 多压监控器
监视电压数目: 3
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 150 ms
电压 - 阀值: 1.05V,1.575V,可调
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-TSSOP(5 引线),SC-88A,SOT-353
供应商设备封装: SC-70-5
包装: 带卷 (TR)
Low-Power Dual-/Triple-Voltage SC70 μP
Supervisory Circuits
Pin Description
PIN
MAX6736 MAX6738 MAX6740 MAX6741 MAX6742
NAME
FUNCTION
MAX6737 MAX6739 MAX6743 MAX6744 MAX6745
Reset Output, Push-Pull or Open Drain Active Low. RESET
changes from high to low when any monitored power-supply
input (V CC 1, V CC 2, RSTIN) drops below its selected reset
threshold. It remains low until all monitored power-supply
inputs exceed their selected reset thresholds for the V CC
reset timeout period. RESET is forced low if MR is low for at
1
1
1
1
1
RESET
least the MR minimum input pulse width. It remains low for
the MR reset timeout period after MR goes high. The push-
pull output is referenced to V CC 1. The MAX6736/MAX6738
open-drain outputs require an external pullup resistor. The
MAX6740/MAX6741/MAX6742 open-drain outputs have an
internal 50k ? pullup resistor to V CC 1 and provide a manual
reset function.
2
2
2
2
2
GND
Ground
Manual Reset, Active Low. Pull low for at least MR minimum
input pulse width to force RESET low. Reset remains active
3
3
MR
as long as MR is low and for the MR reset timeout period
after MR goes high. There is an internal 1.5k ? pullup resistor
to V CC 1.
4
4
4
V CC 2
Voltage Input 1. Power supply and input for the secondary
μP voltage reset monitor.
Adjustable Reset Threshold Input. RESET is asserted when
4
3
RSTIN
RSTIN is below the internal 0.488V reference level. Set the
adjustable reset threshold with an external resistor-divider
network. Connect RSTIN to V CC 1 if unused.
5
5
5
5
5
V CC 1
Voltage Input 2. Power supply and input for the primary μP
voltage reset monitor.
Power-Fail Comparator Input. PFO is asserted when PFI is
below 0.488V. PFO is deasserted without any reset timeout
4
PFI
period when PFI goes above 0.488V. Connect PFI to an
external resistor network to set the desired monitor
threshold.
3
PFO
Power-Fail Comparator Output, Open Drain Active Low. PFO
is asserted when PFI is below 0.488V.
V CC 1 Power-OK Output, Open Drain Active High. POK1
remains low as long as V CC 1 is below V TH 1. POK1 output
3
POK1
goes high after V CC 1 exceeds V TH 1 for the POK1 timeout
period. POK1 logic is independent of the MR or V CC 2 inputs.
The output can be used to control V CC 1-to-V CC 2 supply
sequencing.
8
_______________________________________________________________________________________
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