参数资料
型号: MAX6741XKYDD3+T
厂商: Maxim Integrated Products
文件页数: 12/16页
文件大小: 0K
描述: IC SUPERVISOR MPU SC-70-5
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 多压监控器
监视电压数目: 2
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 150 ms
电压 - 阀值: 0.788V,2.188V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-TSSOP(5 引线),SC-88A,SOT-353
供应商设备封装: SC-70-5
包装: 带卷 (TR)
Low-Power Dual-/Triple-Voltage SC70 μP
Supervisory Circuits
shown in Figure 6. Select the values of R1, R2, and R3
A) V IN IS POSITIVE
such that PFI sees V TH-PFI (488mV) when V EXT falls to
its power-fail trip point (V FAIL ) and when V EXT rises to
V EXT_TH
R1
MAX6742
MAX6745
V EXT_TH = V TH-PFI
(
R1 + R2
R2
)
its power-good trip point (V GOOD ). The hysteresis win-
dow extends between the specified V FAIL and V GOOD
thresholds. R3 adds the additional hysteresis by sink-
R2
B) V IN IS NEGATIVE
PFI
GND
PFO
ing current from the R1/R2 divider network when the
PFO output is logic low and sourcing current into the
network when PFO is logic high. R3 is typically an order
of magnitude greater than R1 or R2.
The current through R2 should be at least 1μA to ensure
that the 10nA (max) PFI input current does not significant-
ly shift the trip points. Therefore, for most applications:
R2 < V TH-PFI / 1mA < 0.488V / 1mA < 488k ?
PFO is an open-drain output requiring an external
pullup resistor, R4. Select R4 to be less than 1% of R3.
( ) (
- CC
V CC
MAX6742
V EXT_TH = R 2
(V TH-PFI )
1 + 1
R 1 R 2
)
V
R 1
V GOOD = DESIRED V EXT GOOD VOLTAGE THRESHOLD
R1
R2
PFI
MAX6745
PFO
V PFI = 488mV
V FAIL = DESIRED V EXT FAIL VOLTAGE THRESHOLD
V PU = V PULLUP (FOR OPEN-DRAIN PFO )
R2 = 488k ? (FOR >1μA R2 CURRENT)
V EXT_TH
( V GOOD - V TH ? PFI ) ?
GND
Figure 4. Using Power-Fail Input to Monitor an Additional
Power Supply
R 1 = R 2
( V TH - PFI ( V GOOD - V FAIL )
V PU
V TH - PFI
Adding Hysteresis to the
Power-Fail Comparator
The power-fail comparator has a typical input hystere-
sis of 2.5mV. This is sufficient for most applications in
which a power-supply line is being monitored through
an external voltage-divider. If additional noise margin is
desired, connect a resistor between PFO and PFI, as
R3 = (R1 x V PU ) / (V GOOD - V FAIL )
R4 ≤ 0.01 x R3
Power Sequencing Applications
Many dual-voltage processors/ASICs require specific
power-up/power-down sequences for the I/O and core
supplies.
V CC 1 V CC 2
RESET TO OTHER SYSTEM COMPONENTS
R3
V PULLUP
V GOOD
V IN
V FAIL
MAX6737
MAX6739
V EXT
MAX6742
MAX6745
PFO
V CC 2
MAX6743
MAX6744 RESET
MAX6745
4.7k ?
RESET
μ P
R1
PFI
PFO
R4
V CC 1
R2
V GOOD = DESIRED V EXT GOOD VOLTAGE THRESHOLD
V FAIL = DESIRED V EXT FAIL VOLTAGE THRESHOLD
V OH = V CC 1 (FOR PUSH-PULL PFO)
R2 = 200k ? (FOR > 2.5 μ A R2 CURRENT)
GND
GND
GND
R1 = R2 ((V GOOD - V TH-PFI ) - (V TH-PFI )(V GOOD - V FAIL ) / V PU ) / V TH-PFI
R3 = (R1 x V OH ) / (V GOOD - V FAIL )
Figure 5. Interfacing to μPs with Bidirectional Reset I/O
Figure 6. Adding Hysteresis to Power Fail for Push-Pull PFO
12
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