参数资料
型号: MAX6752KA28-T
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 电源管理
英文描述: µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封装: SOT-23, 8 PIN
文件页数: 2/14页
文件大小: 170K
代理商: MAX6752KA28-T
MAX6746–MAX6753
Applications Information
Selecting Reset/Watchdog
Timeout Capacitor
The reset timeout period is adjustable to accommodate
a variety of P applications. Adjust the reset timeout
period (tRP) by connecting a capacitor (CSRT) between
SRT and ground. Calculate the reset timeout capacitor
as folllows:
CSRT = tRP / (5.06 x 106)
with tRP in seconds and CSRT in Farads.
The watchdog timeout period is adjustable to accom-
modate a variety of P applications. With this feature,
the watchdog timeout can be optimized for software
execution. The programmer can determine how often
the watchdog timer should be serviced. Adjust the
watchdog timeout period (tWD) by connecting a specif-
ic value capacitor (CSWT) between SWT and GND. For
normal mode operation, calculate the watchdog time-
out capacitor as follows:
CSWT = tWD/(5.06 x 106)
with tRP in seconds and CSRT in Farads.
For the MAX6752 and MAX6753 windowed watchdog
function, calculate the slow watchdog period, tWD2 as
follows:
tWD2 = 0.65 x 109 x CSWT
CSRT and CSWT must be a low-leakage (< 10nA) type
capacitor. Ceramic capacitors are recommended.
Transient Immunity
In addition to issuing a reset to the P during power-up,
power-down, and brownout conditions, these supervi-
sors are relatively immune to short-duration supply tran-
sients (glitches). The Maximum Transient Duration vs.
Reset Threshold Overdrive graph in the
Typical
Operating Characteristics shows this relationship.
The area below the curves of the graph is the region
in which these devices typically do not generate a reset
pulse. This graph was generated using a falling pulse
applied to VCC , starting above the actual reset threshold
(VTH) and ending below it by the magnitude indicated
(reset-threshold overdrive). As the magnitude of the tran-
sient increases (farther below the reset threshold), the
maximum allowable pulse width decreases. Typically, a
VCC transient that goes 100mV below the reset threshold
and lasts 50s or less does not cause a reset pulse to be
issued.
P Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
10
______________________________________________________________________________________
MAX6747
MAX6749
MAX6451
MAX6753
GND
N
RESET
5V
VCC
GND
3.3V
μP
100k
Ω
Figure 6. Interfacing to Other Voltage Levels
WDI
(a) FAST FAULT
(b) SLOW FAULT
WDI
RESET
(c) NORMAL OPERATION (NO PULSING, OUTPUT STAYS HIGH)
RESET
WDI
RESET
tWDI < tWD1 (MIN)
tWDI > tWD2 (MAX)
tWD1 (MAX) < tWDI < tWD2 (MIN)
Figure 5. MAX6752/MAX6753 Window Watchdog Diagram
相关PDF资料
PDF描述
MAX6752KA30-T &#181;P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay
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MAX6752KA32-T &#181;P Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay
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