参数资料
型号: MAX6805US36D2+T
厂商: Maxim Integrated Products
文件页数: 4/8页
文件大小: 0K
描述: IC RESET MPU LOW PWR SOT143-4
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 20 ms
电压 - 阀值: 3.6V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: TO-253-4,TO-253AA
供应商设备封装: SOT-143-4
包装: 带卷 (TR)
4-Pin, Low-Power
μP Reset Circuits with Manual Reset
Pin Description
PIN
MAX6803
1
MAX6804
MAX6805
1
NAME
GND
Ground
FUNCTION
Active-Low Reset Output. RESET is asserted while V CC is below the reset
threshold, or while MR is asserted. RESET remains asserted for a reset
2
RESET
timeout period (t RP ) after V CC rises above the reset threshold or MR is
deasserted. RESET on the MAX6804 is push/pull. RESET on the MAX6805
is open-drain.
Active-High Reset Output. RESET is asserted high while V CC is below the
2
RESET
reset threshold or while MR is asserted, and RESET remains asserted for a
reset timeout period (t RP ) after V CC rises above the reset threshold or MR
is deasserted. RESET on the MAX6803 is push/pull.
Manual Reset Input. A logic low on MR asserts reset. Reset remains
3
3
MR
asserted as long as MR is low, and for the reset timeout period (t RP ) after
MR goes high. Leave unconnected or connect to V CC if not used.
4
4
V CC
Supply Voltage Input
Applications Information
Manual Reset Input
Many μP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic low on MR
asserts reset. Reset remains asserted while MR is low,
and for the reset active timeout period after MR returns
high. MR has an internal 20k ? pullup resistor, so it can
be left unconnected if not used. Connect a normally
open momentary switch from MR to GND to create a
manual reset function; external debounce circuitry is
not required.
Interfacing to μPs with
Bidirectional Reset Pins
Since the RESET output on the MAX6805 is open-drain,
shows the maximum pulse width that a negative-going
V CC transient may typically have without issuing a reset
signal. As the amplitude of the transient increases, the
maximum allowable pulse width decreases.
Ensuring a Valid Reset Output
down to V CC = 0
When V CC falls below 1V and approaches the minimum
operating voltage of 0.7V, push/pull-structured reset
sinking (or sourcing) capabilities decrease drastically.
High-impedance CMOS-logic inputs connected to the
RESET pin can drift to indeterminate voltages. This
does not present a problem in most cases, since most
V CC
this device interfaces easily with μPs that have bidirec-
tional reset pins, such as the Motorola 68HC11.
Connecting the μP supervisor’s RESET output directly
V CC
100k ?
V CC
μ P
to the microcontroller’s (μC’s) RESET pin with a single
pullup resistor allows either device to assert reset
(Figure 1).
MR
MAX6805
RESET
MOTOROLA
68HCXX
RESET
Negative-Going V CC Transients
In addition to issuing a reset to the μP during power-up,
power-down, and brownout conditions, these devices
are relatively immune to short-duration, negative-going
V CC transients (glitches). The Typical Operating
Characteristics show the Maximum Transient Duration
GND
GND
vs. Reset Comparator Overdrive graph. The graph
Figure 1. Interfacing to μPs with Bidirectional Reset Pins
4
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