参数资料
型号: MAX6820UT+T
厂商: Maxim Integrated Products
文件页数: 5/8页
文件大小: 0K
描述: IC SEQUENCER POWER SOT23-6
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
类型: 序列发生器
监视电压数目: 2
复位超时: 最小为 140 ms
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SOT-23-6
供应商设备封装: SOT-6
包装: 标准包装
产品目录页面: 1423 (CN2011-ZH PDF)
其它名称: MAX6820UT+TDKR
SOT23 Power-Supply Sequencers
Pin Description
PIN
NAME
FUNCTION
MAX6819
MAX6820
1
2
3
1
2
3
V CC1
GND
SETV
Supply Voltage 1. Either V CC1 or V CC2 must be greater than the UVLO to enable
external MOSFET drive.
Ground
Sequence Threshold Set. Connect to an external resistor-divider network to set the
V CC1 threshold that enables GATE turn-on. The internal reference is 0.618V.
Active-High Enable. GATE drive is enabled t DELAY after EN is driven high. GATE
4
EN
drive is immediately disabled when EN is driven low. Connect to the higher of V CC1
and V CC2 if not used.
4
SETD
GATE Delay Set Input. Connect an external capacitor from SETD to GND to adjust
the delay from SETV > V TH to GATE turn-on. t DELAY (s) = 2.484 x 10 6 x C SET (F).
GATE Drive Output. GATE drives an external n-channel MOSFET to connect V CC2 to
the load. GATE drive enables t DELAY after SETV exceeds V TH and ENABLE is driven
5
5
GATE
high. GATE drive is immediately disabled when SETV drops below V TH or ENABLE is
driven low. When enabled, an internal charge pump drives GATE to V CC2 + 5.5V to
fully enhance the external n-channel MOSFET.
6
6
V CC2
Supply Voltage 2. Either V CC1 or V CC2 must be greater than the UVLO to enable
external MOSFET drive.
Detailed Description
Many dual-supply processors or multivoltage boards
require one power supply to rise to the proper operat-
ing voltage before another supply is applied. Improper
sequencing can lead to chip latchup, incorrect device
initiation, or long-term reliability degradation. If the vari-
ous supply voltages are not locally generated (coming
from a main system bus, an externally purchased silver
box, or a nonsequenced power management chip),
V CC1
UVLO
V CC2
GATE
V CC2 OUT
power-on and power-off sequencing can be difficult to
control or predict. Supply loading can affect turn-
on/turn-off times from board to board.
The MAX6819/MAX6820 provide proper local voltage
SETV
0.62V
SEQUENCE
DELAY/
LOGIC
GATE DRIVE
CHARGE PUMP
sequencing in multisupply systems. The sequencers use
an external n-channel MOSFET to switch the secondary
supply to the load only when the primary supply is above
GND
a desired operating voltage threshold. The n-channel
MOSFET operates in a default off mode when the primary
( ) FOR MAX6820 ONLY
EN (SETD)
supply is below the desired threshold or if neither supply
exceeds the sequencer’s UVLO level.
When the primary supply voltage is above the set
threshold, the external MOSFET is driven on. An inter-
nal charge pump fully enhances the external MOSFET
by providing a gate-to-source voltage (V GS ) of +5.5V
(typ). The charge pump fully enhances the MOSFET to
yield a low drain-to-source impedance (R DS(ON) ) for
reduced switch voltage drop. The MOSFET is never dri-
Figure 1. Functional Diagram
ven on unless the sequencer can provide a minimum
V GS enhancement, ensuring that the switch MOSFET
never operates in its higher impedance linear range.
Either supply may act as the primary source, regard-
less of the voltage level, provided that V CC1 or V CC2 is
greater than 2.125V (Figure 1 and Figure 2).
_______________________________________________________________________________________
5
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