参数资料
型号: MAX6890ETI
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 电源管理
英文描述: EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
中文描述: 6-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQCC28
封装: 5 X 5 MM, TQFN-28
文件页数: 25/40页
文件大小: 255K
代理商: MAX6890ETI
MAX6889/MAX6890/MAX6891
EEPROM-Programmable, Octal/Hex/Quad,
Power-Supply Sequencers/Supervisors
______________________________________________________________________________________
31
MAX6889/MAX6890/MAX6891MAX6889/MAX6890/MAX6891MAX6889/MAX6890/MAX6891
master device to generate a clock signal. The master
device (typically a microcontroller) generates SCL and ini-
tiates data transfer on the bus.
A master device communicates to the MAX6889/
MAX6890/MAX6891 by transmitting the proper address
followed by command and/or data words. Each trans-
mit sequence is framed by a START (S) or REPEATED
START (SR) condition and a STOP (P) condition. Each
word transmitted over the bus is 8 bits long and is
always followed by an acknowledge pulse.
SCL is a logic input, while SDA is an open-drain
input/output. SCL and SDA both require external pullup
resistors to generate the logic-high voltage. Use 4.7k
resistors for most applications.
Bit Transfer
Each clock pulse transfers one data bit. The data on
SDA must remain stable while SCL is high (Figure 4),
otherwise the MAX6889/MAX6890/MAX6891 register a
START or STOP condition (Figure 5) from the master.
SDA and SCL idle high when the bus is not busy.
Start and Stop Conditions
A master device signals the beginning of a transmission
with a START (S) condition (Figure 5) by transitioning
SDA from high to low while SCL is high. The master
device issues a STOP (P) condition (Figure 5) by transi-
tioning SDA from low to high while SCL is high. A STOP
condition frees the bus for another transmission. The bus
remains active if a REPEATED START condition is gener-
ated, such as in the read byte or block read protocol
(see Figure 8). Both SCL and SDA are high when the bus
is not busy.
Early STOP Conditions
The MAX6889/MAX6890/MAX6891 recognize a STOP
condition at any point during transmission except if a
STOP condition occurs in the same high pulse as a
START condition. This condition is not a legal I2C for-
mat. At least one clock pulse must separate any START
and STOP condition.
Repeated START Conditions
A REPEATED START (SR) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation (see Figure 8). SR may also be used
when the bus master is writing to several I2C devices
and does not want to relinquish control of the bus. The
MAX6889/MAX6890/MAX6891 serial interface supports
continuous write operations with or without an SR condi-
tion separating them. Continuous read operations
require SR conditions because of the change in direction
of data flow.
Acknowledge
The acknowledge bit (ACK) is the 9th bit attached to any
8-bit data word. The receiving device always generates
an ACK. The MAX6889/MAX6890/MAX6891 generate an
ACK when receiving an address or data by pulling SDA
low during the 9th clock period (Figure 6). When trans-
mitting data, such as when the master device reads data
back from the MAX6889/MAX6890/MAX6891, the
MAX6889/MAX6890/MAX6891 wait for the master device
to generate an ACK. Monitoring ACK allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if the receiving device is busy or if a sys-
tem fault has occurred. In the event of an unsuccessful
DATA LINE STABLE,
DATA VALID
SDA
SCL
CHANGE OF
DATA ALLOWED
Figure 4. Bit Transfer
P
S
START
CONDITION
SDA
SCL
STOP
CONDITION
Figure 5. Start and Stop Conditions
相关PDF资料
PDF描述
MAX6891ETP EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
MG200-BCG24HD T-1 3/4 SINGLE COLOR LED, GREEN, 5.1 mm
MG200-BCG24H T-1 3/4 SINGLE COLOR LED, GREEN, 5.1 mm
MG200-BCG28HD T-1 3/4 SINGLE COLOR LED, GREEN, 5.1 mm
MG200-BCG5H T-1 3/4 SINGLE COLOR LED, GREEN, 5.1 mm
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