参数资料
型号: MAX6891ETP
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 电源管理
英文描述: EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
中文描述: 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQCC20
封装: 5 X 5 MM, TQFN-20
文件页数: 8/40页
文件大小: 255K
代理商: MAX6891ETP
MAX6889/MAX6890/MAX6891
EEPROM-Programmable, Octal/Hex/Quad,
Power-Supply Sequencers/Supervisors
16
______________________________________________________________________________________
MARGIN
MARGIN allows system-level testing while power sup-
plies exceed the normal ranges. Driving MARGIN low
forces the programmable outputs to hold the last state
while system-level testing occurs. Leave MARGIN
unconnected or connect to DBP if unused. An internal
10A current source pulls MARGIN to DBP. The state of
each programmable output does not change while
MARGIN = GND. MARGIN overrides MR if both assert
at the same time.
Programmable Outputs
The MAX6889 features ten programmable outputs, the
MAX6890 features eight programmable outputs, and
the MAX6891 features five programmable outputs.
Selectable output stage configurations include: active-
low or active-high, open drain, or weak pullup. During
power-up, the programmable outputs pull to GND with
an internal 10A current sink for 1V < VCC < VUVLO.
The programmable outputs remain in their active states
until their respective PO timeout period expires, and all
of the programmed conditions are met for each output.
Any output programmed to depend on no condition
always remains in its active state (Table 17). An output
configured as active-high is considered asserted when
that output is logic-high.
The voltage monitors generate fault signals (logical 0) to
the MAX6889/MAX6890/MAX6891s’ logic array when an
input voltage is below the programmed undervoltage
threshold. For example, the PO3 (Table 9) programmable
output may depend on the IN1 undervoltage threshold,
and the state of GPI1. Write “1”s to R10h[0] and R11h[1]
to configure as indicated. IN1 must be above the under-
voltage threshold (Table 2) and GPI1 must be inactive
(Table 5) to be a logic “1,” then PO3 deasserts. The logic
state of PO3, in this example, is equivalent to the logical
statement: “V1 GPI1.”
Registers 0Ah through 27h configure each of the pro-
grammable outputs. Programmable timing blocks set
the PO_ timeout period from 25s to 1600ms for each
programmable output. See Table 17 to set the active
state (active-high or active-low) for each programmable
output and Tables 18 and 19 to select the output stage
types, and PO_ timeout periods for each output. Each
programmable output allows a different set of condi-
tions to assert each output as shown in Tables 7–16.
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT
RANGE
DESCRIPTION
07h
87h
[7:0]
IN8 undervoltage detector threshold (V8) (see equations in the Inputs section)
08h
88h
[7]
IN8 range selection.
0 = 2.5V to 15.25V range in 50mV increments.
1 = 1.25V to 7.625V range in 25mV increments.
09h
89h
[7]
IN8 input impedance. 0 = normal mode. 1 = high-Z mode, with a 0.1667V to 1.0167V
range in 3.3mV increments.
Table 4. IN8 Threshold Settings
REGISTER
ADDRESS
EEPROM
ADDRESS
BIT
RANGE
DESCRIPTION
[0]
GPI1. 0 = active-low, 1 = active-high.
[1]
GPI2. 0 = active-low, 1 = active-high.
[2]
GPI3. 0 = active-low, 1 = active-high.
28h
A8h
[3]
GPI4 (MAX6889/MAX6890 only). 0 = active-low, 1 = active-high.
Table 5. GPI1–GPI4 Active Logic States
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