参数资料
型号: MAX6892ETJ+T
厂商: Maxim Integrated Products
文件页数: 7/19页
文件大小: 0K
描述: IC SEQ/SUPERVISOR OCT 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 序列发生器
监视电压数目: 8
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 可调节/可选择
电压 - 阀值: 8 种可选阀值组合
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
Pin Description
MAX6892
PIN
MAX6893
MAX6894
NAME
FUNCTION
Open-Drain, Power-Good Output 2. PG2 asserts low when the voltage input at
1
1
1
PG2
IN2 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG2 deasserts with a factory preset timeout period of 6.25ms.
Open-Drain, Power-Good Output 3. PG3 asserts low when the voltage input at
2
2
2
PG3
IN3 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG3 deasserts with a factory preset timeout period of 6.25ms.
Open-Drain, Power-Good Output 4. PG4 asserts low when the voltage input at
3
3
3
PG4
IN4 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG4 deasserts with a factory preset timeout period of 6.25ms.
4
4
4
GND
Ground
Open-Drain, Power-Good Output 5. PG5 asserts low when the voltage input at
5
5
PG5
IN5 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG5 deasserts with a factory preset timeout period of 6.25ms.
Open-Drain, Power-Good Output 6. PG6 asserts low when the voltage input at
6
6
PG6
IN6 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG6 deasserts with a factory preset timeout period of 6.25ms.
Open-Drain, Power-Good Output 7. PG7 asserts low when the voltage input at
7
PG7
IN7 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG7 deasserts with a factory preset timeout period of 6.25ms.
Open-Drain, Power-Good Output 8. PG8 asserts low when the voltage input at
8
PG8
IN8 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG8 deasserts with a factory preset timeout period of 6.25ms.
Open-Drain, Active-Low Reset Output Stage. RESET asserts low when any
9
7
7
RESET
monitored input (IN_) is below the selected threshold or manual reset ( MR ) is
pulled low. RESET remains low for the reset timeout period after all reset-
causing conditions are cleared, and then deasserts.
Open-Drain, Active-Low Watchdog Output Stage. If WDI remains high or low for
longer than the watchdog timeout period, the internal watchdog timer runs out
10
8
8
WDO
and the WDO output asserts low. The internal watchdog timer clears whenever
RESET is asserted or WDI sees a rising or falling edge. Connect WDO to MR to
automatically assert the RESET output after each watchdog timeout fault.
Margin Input. MARGIN holds PG_, RESET , and WDO in their existing states
11
9
9
MARGIN
when driven low. Leave MARGIN unconnected or connect to DBP if unused.
MARGIN overrides MR if both assert at the same time. MARGIN is internally
pulled up to DBP through a 10μA current source.
Active-Low Manual Reset Input. Pull MR low to assert RESET . RESET remains
12
10
10
MR
asserted for its preset/adjustable reset timeout period when MR is driven/pulled
high. MR is internally pulled up to DBP through a 10μA current source.
Threshold Selection Input 0. Logic input to select desired thresholds. Connect
13
11
11
TH0
TH0 to GND or DBP. See Table 2 for available thresholds. Input has no internal
pullup or pulldown.
_______________________________________________________________________________________
7
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