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| 型号： | MAX6894ETI+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/19页 |
| 文件大小： | 0K |
| 描述： | IC SEQUENCE/SUPERVISOR 28TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 类型： | 序列发生器 |
| 监视电压数目： | 4 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 管件 |
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
Manual Reset ( MR )
Many μP-based products require manual reset capabil-
ity to allow an operator or external logic circuitry to initi-
ate a reset. The manual reset input ( MR ) can connect
directly to a switch without an external pullup resistor or
debouncing network. MR is internally pulled up to DBP
through a 10μA current source and, therefore, can be
left unconnected if unused.
MR is designed to reject fast falling transients (typically
100ns pulses) and it must be held low for a minimum of
1μs to assert RESET . After MR transitions from low to
high, RESET remains asserted for the duration of the
reset timeout period.
Margin Output Disable ( MARGIN )
MARGIN allows system-level testing while power sup-
plies exceed the normal ranges. Driving MARGIN low
forces PG_, RESET , and WDO to hold the last state
while system-level testing occurs. Leave MARGIN
unconnected or connect to DBP if unused. An internal
10μA current source pulls MARGIN to DBP. The state of
each programmable output, RESET , and WDO does
not change while MARGIN = GND.
Enable Input
ENABLE is an active-low, logic input. Driving ENABLE
high pulls all PG_ low. Drive ENABLE low or leave
unconnected for normal operation. ENABLE is internally
pulled down to GND through a 10μA current sink.
Power-Good Outputs
The MAX6892 features eight power-good outputs, the
MAX6893 features six power-good outputs, and the
MAX6894 features four power-good outputs. Each out-
put (PG_) responds to its respective input (IN_). Each
PG_ is open drain. During power-up, the outputs pull
down to GND with an internal 10μA current sink for 1V
< V CC < V UVLO .
R E S E T Output
The reset output is typically connected to the reset
input of a μP. A μP’s reset input starts or restarts the μP
in a known state. The MAX6892/MAX6893/MAX6894
supervisory circuits provide the reset logic to prevent
code-execution errors during power-up, power-down,
and brownout conditions.
RESET changes from high to low whenever one or more
input voltage (IN1 –IN8) monitors drop below their
respective reset threshold voltage or when MR is pulled
low for a minimum of 1μs. Once the affected input volt-
age monitor(s) exceeds its respective reset threshold
voltage(s), RESET remains low for the reset timeout
period, then deaaserts.
Applications Information
Selecting the Reset/Watchdog
Timeout Capacitor
The reset timeout period can be adjusted to accommo-
date a variety of μP applications. Adjust the reset time-
out period (t RP ) by connecting a capacitor (C SRT )
between SRT and ground. Calculate the reset timeout
capacitor as follows:
C SRT = t RP /(4.348 x 106)
with t RP in seconds and C SRT in Farads. Connect SRT
to V CC for a factory-programmed reset timeout of
200ms (typ).
The watchdog timeout period can be adjusted to
accommodate a variety of μP applications. With this
feature, the watchdog timeout can be optimized for
software execution. The programmer can determine
how often the watchdog timer should be serviced.
Adjust the watchdog timeout period (t WD ) by connect-
ing a specific value capacitor (C SWT ) between SWT
and GND. For normal mode operation, calculate the
watchdog timeout capacitor as follows:
C SWT = t WD /(4.348 x 10 6 )
with t WD in seconds and C SWT in Farads. Connect SWT
to V CC for a factory-programmed watchdog timeout of
1.6s (normal mode) and 102.4s (initial mode).
C SRT and C SWT must be a low-leakage (< 10nA) type
capacitor. Ceramic capacitors are recommended.
Layout and Bypassing
For better noise immunity, bypass each of the voltage
detector inputs to GND with 0.1μF capacitors installed
as close to the device as possible. Bypass V CC and
DBP to GND with 1μF capacitors installed as close to
the device as possible.
______________________________________________________________________________________
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX6894ETI+ | 功能描述:监控电路 Pin-Selectable Quad Power Supply Sequenc RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| MAX6894ETI+T | 功能描述:监控电路 Pin-Selectable Quad Power Supply Sequenc RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| MAX6894ETI-T | 功能描述:监控电路 RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| MAX6895AALT | 制造商:Maxim Integrated Products 功能描述:ULTRA-SMALL ADJUSTABLE SEQUENCING/ - Rail/Tube |
| MAX6895AALT/GH9 | 制造商:Maxim Integrated Products 功能描述:ULTRA-SMALL, ADJUSTABLE SEQUENCING/SUPERVISORY CIRCUITS - Rail/Tube |
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