参数资料
型号: MAX6894ETI+T
厂商: Maxim Integrated Products
文件页数: 14/19页
文件大小: 0K
描述: IC SEQUENCE/SUPERVISOR 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 序列发生器
监视电压数目: 4
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 可调节/可选择
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
Watchdog Timer
The MAX6892/MAX6893/MAX6894s’ watchdog circuit
monitors the microprocessor’s (μP’s) activity. If the μP
does not toggle the watchdog input (WDI) within the
watchdog timeout period, the watchdog output ( WDO )
asserts. The internal watchdog timer is cleared by
RESET , or by a transition at WDI (which can detect
pulses as short as 50ns). The watchdog timer remains
cleared while reset is asserted. The timer starts count-
ing as soon as WDO is released (see Figure 2).
The MAX6892/MAX6893/MAX6894 feature two modes
of watchdog timer operation: normal mode and initial
mode. At power-up, after a reset event, or after the
watchdog timer expires, the initial watchdog timeout is
active. After the first transition on WDI, the normal
watchdog timeout is active. The initial and normal
watchdog timeouts are determined by the value of the
capacitor connected between SWT and ground or by
connecting SWT to V CC (see the Selecting the Reset and
2.5V
V CC OR IN2–IN5
WDO
RESET
WDI
Watchdog Timeout Capacitor section). The initial watch-
dog timeout is approximately 64 times the normal watch-
dog timeout. For example, in initial mode a 1μF capacitor
gives a watchdog timeout period of about 5min.
If WDO is connected to MR, the WDO asserts for a
short duration (~5μs), long enough to assert the RESET
output. Asserting RESET clears the watchdog timer and
WDO goes high. The reset output remains asserted for
its timeout period after a watchdog fault. The watchdog
timer stays cleared as long as RESET is low.
The watchdog timeout period is determined by the
value of the capacitor connected between SWT and
ground (see the Selecting the Reset/Watchdog Timeout
Capacitor section). Connect SWT to DBP to select fac-
tory-programmed watchdog timeout. To disable the
watchdog timer connect SWT to GND.
t D-PO
t RP
*t WDI
t WD
*t WDI
WDO NOT CONNECTED TO MR
2.5V
V CC OR IN2–IN5
WDO
RESET
WDI
t D-PO
t RP
*t WDI
t WD
t RP
*t WDI
*t WDI IS THE INITIAL WATCHDOG TIMEOUT PERIOD.
Figure 2. Watchdog, Reset, and Power-Up Timing Diagram
WDO CONNECTED TO MR.
14
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