参数资料
型号: MAX690ACSA
厂商: Maxim Integrated Products
文件页数: 6/12页
文件大小: 0K
描述: IC MPU SUPERVISORY CIRCUIT 8SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
类型: 备用电池电路
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.65V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
Microprocessor Supervisory Circuits
V BATT
BATTERY-SWITCHOVER
CIRCUITRY
V OUT
V CC
+5V
V CC
0V
3.5V
1.25V
RESET
GENERATOR
RESET
(RESET)
V OUT
0V
+5V
RESET
3.0V
t RS
0V
WDI
WATCHDOG
TIMER
+5V
(RESET)
3.0V
0V
MAX690A
0.8V
MAX692A
+5V
PFI
MAX802L
MAX802M
MAX805L
PFO
PFO
0V
1.25V
V BATT = PFI = 3.0V
( ) ARE FOR MAX805L ONLY.
GND
( ) ARE FOR MAX805L ONLY.
I OUT = 0mA
Figure 1. Block Diagram
_______________Detailed Description
Reset Output
A microprocessor’s (μP’s) reset input starts the μP in a
known state. When the μP is in an unknown state, it should
be held in reset. The MAX690A/MAX692A/MAX802L/
MAX802M assert reset during power-up and prevent code
execution errors during power-down or brownout condi-
tions.
On power-up, once V CC reaches 1V, RESET is guaran-
teed to be a logic low. As V CC rises, RESET remains
low. When V CC exceeds the reset threshold, an internal
timer keeps RESET low for a time equal to the reset
pulse width; after this interval, RESET goes high (Figure
2). If a brownout condition occurs (if V CC dips below
the reset threshold), RESET is triggered. Each time
RESET is triggered, it stays low for the reset pulse width
interval. Any time V CC goes below the reset threshold,
the internal timer restarts the pulse. If a brownout con-
dition interrupts a previously initiated reset pulse, the
reset pulse continues for another 200ms. On power-
down, once V CC goes below the threshold, RESET is
guaranteed to be logic low until V CC droops below 1V.
RESET is also triggered by a watchdog timeout. If a
high or low is continuously applied to the WDI pin for
1.6sec, RESET pulses low. As long as RESET is assert-
Figure 2. Timing Diagram
ed, the watchdog timer remains clear. When RESET
comes high, the watchdog resumes timing and must be
serviced within 1.6sec. If WDI is tied high or low, a
RESET pulse is triggered every 1.8sec (t WD plus t RS ).
The MAX805L active-high RESET output is the inverse
of the MAX690A/MAX692A/MAX802L/MAX802M RESET
output, and is guaranteed to be valid with V CC down to
1.1V. Some μPs, such as Intel’s 80C51, require an
active-high reset pulse.
Watchdog Input
The watchdog circuit monitors the μP’s activity. If the
μP does not toggle the watchdog input (WDI) within
1.6sec, a reset pulse is triggered. The internal 1.6sec
timer is cleared by either a reset pulse or by open cir-
cuiting the WDI input. As long as reset is asserted or
the WDI input is open circuited, the timer remains
cleared and does not count. As soon as reset is
released or WDI is driven high or low, the timer starts
counting. It can detect pulses as short as 50ns.
Power-Fail Comparator
The PFI input is compared to an internal 1.25V refer-
ence. If PFI is less than 1.25V, PFO goes low. The
power-fail comparator is intended for use as an under-
voltage detector to signal a failing power supply; it
need not be dedicated to this function though, as it is
6
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