参数资料
型号: MAX691AEUE+T
厂商: Maxim Integrated Products
文件页数: 8/17页
文件大小: 0K
描述: IC SUPERVISOR MPU 16-TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 备用电池电路
监视电压数目: 1
输出: 推挽式,推挽式
复位: 高有效/低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.65V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 带卷 (TR)
Microprocessor Supervisory Circuits
WDI
RESET
15
TO μ P RESET
WDO
MAX691A
MAX693A
1k Ω
RESET
t 1
t 2
t 1
t 3
t 1 = RESET TIMEOUT PERIOD
t 2 = NORMAL WATCHDOG TIMEOUT PERIOD
t 3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER RESET
period. The watchdog function is disabled and WDO is
Figure 1.  Adding an external pulldown resistor ensures
– — — — — –
R E S E T is valid with V CC down to GND.
RESET and RESET are asserted when V CC falls below
the reset threshold (4.65V for the MAX691A/MAX800L,
4.4V for the MAX693A/MAX800M) and remain asserted
for 200ms typ after V CC rises above the reset threshold
on power-up (Figure 5). The devices ’ battery-
switchover comparator does not affect reset assertion.
However, both reset outputs are asserted in battery-
backup mode since V CC must be below the reset
threshold to enter this mode.
Watchdog Function
The watchdog monitors μP activity via the Watchdog
Input (WDI). If the μP becomes inactive, RESET and
RESET are asserted. To use the watchdog function,
connect WDI to a bus line or μP I/O line. If WDI
remains high or low for longer than the watchdog time-
out period (1.6s nominal), WDO , RESET, and RESET
are asserted (see RESET and RESET Outputs section,
and the Watchdog Output discussion on this page).
Watchdog Input
A change of state (high to low, low to high, or a mini-
mum 100ns pulse) at the WDI during the watchdog
period resets the watchdog timer. The watchdog
default timeout is 1.6s.
To disable the watchdog function, leave WDI floating.
An internal resistor network (100k Ω equivalent imped-
ance at WDI) biases WDI to approximately 1.6V.
Internal comparators detect this level and disable the
watchdog timer. When V CC is below the reset thresh-
old, the watchdog function is disabled and WDI is dis-
connected from its internal resistor network, thus
becoming high impedance.
Figure 2. Watchdog Timeout Period and Reset Active Time
Watchdog Output
The Watchdog Output ( WDO ) remains high if there is a
transition or pulse at WDI during the watchdog timeout
a logic high when V CC is below the reset threshold, bat-
tery-backup mode is enabled, or WDI is an open circuit.
In watchdog mode, if no transition occurs at WDI during
the watchdog timeout period, RESET and RESET are
asserted for the reset timeout period (200ms typical).
WDO goes low and remains low until the next transition
at WDI (Figure 2). If WDI is held high or low indefinitely,
RESET and RESET will generate 200ms pulses every
1.6s. WDO has a 2 x TTL output characteristic.
Selecting an Alternative
Watchdog and Reset Timeout Period
The OSC SEL and OSC IN inputs control the watchdog
and reset timeout periods. Floating OSC SEL and OSC
IN or tying them both to V OUT selects the nominal 1.6s
watchdog timeout period and 200ms reset timeout peri-
od. Connecting OSC IN to GND and floating or connect-
ing OSC SEL to V OUT selects the 100ms normal
watchdog timeout delay and 1.6s delay immediately
after reset. The reset timeout delay remains 200ms
(Figure 2). Select alternative timeout periods by con-
necting OSC SEL to GND and connecting a capacitor
between OSC IN and GND, or by externally driving OSC
IN (Table 1 and Figure 3). OSC IN is internally connect-
ed to a ±100nA (typ) current source that charges and
discharges the timing capacitor to create the oscillator
frequency, which sets the reset and watchdog timeout
periods (see Connecting a Timing Capacitor at OSC IN
in the Applications Information section).
8
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