参数资料
型号: MAX6920AWP+T
厂商: Maxim Integrated
文件页数: 7/10页
文件大小: 0K
描述: IC DRVR VFD TUBE SRL 20-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1,000
显示器类型: 真空荧光 (VF)
接口: 4 线串行
电流 - 电源: 1mA
电源电压: 8 V ~ 76 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
供应商设备封装: 20-SOIC W
包装: 带卷 (TR)
12-Output, 76V, Serial-Interfaced
VFD Tube Driver
Table 1. 4-Wire Serial Interface Truth Table
DATA
SERIAL CLOCK SHIFT REGISTER CONTENTS LOAD
INPUT INPUT
LATCH CONTENTS
BLANKING
INPUT
OUTPUT CONTENTS
INPUT
DIN
H
L
X
CLK D0 D1 D2 … Dn-1 Dn LOAD D0 D1 D2
H
R0 R1 … Rn-2 Rn-1
L
R0 R1 … Rn-2 Rn-1
R0
R1 R2 … Rn-1
Rn
… Dn-1 Dn BLANK D0 D1 D2
Dn-1 Dn
X
X
X
X
X
L
R0 R1 R2
… Rn-1 Rn
P0
P1
P2 … Pn-1
Pn
H
P0
X
P1
X
P2
X
… Pn-1 Pn
X
X
L
H
P0
L
P1 P2
L
L
Pn-1
L
Pn
L
L = Low logic level.
H = High logic level.
X = Don’t care.
P = Present state (shift register).
R = Previous state (latched).
?
?
DIN is the interface data input, and must be stable
when it is sampled on the rising edge of CLK.
DOUT is the interface data output, which shifts
LOAD may be high or low during a transmission. If
LOAD is high, then the data shifted into the shift regis-
ter at DIN appears at the OUT0 to OUT11 outputs.
data out from the MAX6920 ’ s 12-bit shift register
on the falling edge of CLK. Data at DIN is propa-
gated through the shift register and appears at
DOUT (20 CLK cycles + t DO ) later.
A fifth input pin, BLANK, can be taken high to force out-
puts OUT0 to OUT11 low, without altering the contents
of the output latches. When the BLANK input is low,
outputs OUT0 to OUT11 follow the state of the output
latches. A common use of the BLANK input is PWM
intensity control.
The BLANK input ’ s function is independent of the oper-
ation of the serial interface. Data can be shifted into the
serial interface shift register and latched regardless of
the state of BLANK.
Writing Device Registers Using the 4-Wire
Serial Interface
The MAX6920 is written using the following sequence:
1) Take CLK low.
2) Clock 12 bits of data in order D11 first to D0 last
into DIN, observing the data setup and hold times.
CLK and DIN may be used to transmit data to other
peripherals. Activity on CLK always shifts data into the
MAX6920 ’ s shift register. However, the MAX6920 only
updates its output latch on the rising edge of LOAD,
and the last 12 bits of data are loaded. Therefore, multi-
ple devices can share CLK and DIN as long as they
have unique LOAD controls.
Determining Driver Output Voltage Drop
The outputs are CMOS drivers, and have a resistive
characteristic. The typical and maximum sink and
source output resistances can be calculated from the
V H and V L electrical characteristics. Use this calculated
resistance to determine the output voltage drop at dif-
ferent output currents.
Output Current Ratings
The continuous current source capability is 40mA per
output. Outputs may drive up to 75mA as a repetitive
peak current, subject to the on time (output high) being
no longer than 1ms, and the duty cycle being such that
the output power dissipation is no more than the dissipa-
tion for the continuous case. The repetitive peak rating
3)
Load the 12 output latches with a falling edge
on LOAD.
allows outputs to drive a higher current in multiplex grid
driver applications, where only one grid is on at a time,
and the multiplex time per grid is no more than 1ms.
_______________________________________________________________________________________
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