参数资料
型号: MAX6946ATE+
厂商: Maxim Integrated
文件页数: 7/24页
文件大小: 0K
描述: IC LED DRIVER LINEAR 16-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
恒定电流:
拓扑: 开路漏极,PWM
输出数: 10
内部驱动器:
类型 - 主要: 背光
类型 - 次要: RGB,白色 LED
频率: 400kHz
电源电压: 2.25 V ~ 3.6 V
输出电压: 7V
安装类型: 表面贴装
封装/外壳: 16-WFQFN 裸露焊盘
供应商设备封装: 16-TQFN(3x3)
包装: 管件
工作温度: -40°C ~ 125°C
10-Port, Constant-Current LED Driver and
I/O Expander with PWM Intensity Control
Detailed Description
Table 1. Register Address Map
The MAX6946/MAX6947 general-purpose input/output
(GPIO) peripherals provide 10 I/O ports, P0 to P9, con-
trolled through an I 2 C-compatible serial interface. Use
the 10 I/O ports as logic inputs, open-drain logic out-
puts, or constant-current sinks in any combination.
Ports withstand 7V independent of the MAX6946/
MAX6947s ’ supply voltage whether used as logic
inputs, logic outputs, or constant-current sinks.
The MAX6946/MAX6947 feature shutdown and standby
modes for low-power dissipation. The I/O ports feature
pulse-width modulation (PWM) of the outputs and can
stagger the PWM timing of the 10 port outputs in con-
secutively phased 45° increments. The I/O ports also
feature ramp-up and ramp-down controls.
The MAX6946/MAX6947 feature a RST input to halt any
serial-interface transmission and bring the device out of
shutdown.
Open-drain logic outputs require external pullup resis-
tors to provide the logic-high reference. Ports config-
ured as open-drain logic outputs have a relatively weak
sink capability, but are still adequate for normal logic-
level outputs. The weak drive means that the short-cir-
cuit current is low enough that inadvertently driving an
LED from a port configured as a logic output is unlikely
to damage the LED.
The MAX6946 features a fixed I 2 C slave address of
010 0000 and provides an OSC input to accept an
external PWM clock input as an alternative to the inter-
nal PWM clock.
The MAX6947 features an AD0 input that uses two-level
logic to select from two I 2 C slave addresses. The
MAX6947 always uses the internal PWM clock.
Register Structure
The MAX6946/MAX6947 contain 22 internal registers
(see Table 1). Use registers 0x00 to 0x09 to individually
control ports P0 to P9. Registers 0x0A to 0x0D allow
more than one port control register to be written with
the same data to simplify software. Registers 0x0E and
0x0F do not store data, but return the port input status
when read. Registers 0x10 to 0x15 configure and con-
trol the device operation.
DESCRIPTION
Port P0 output level or PWM
Port P1 output level or PWM
Port P2 output level or PWM
Port P3 output level or PWM
Port P4 output level or PWM
Port P5 output level or PWM
Port P6 output level or PWM
Port P7 output level or PWM
Port P8 output level or PWM
Port P9 output level or PWM
Write ports P0–P9 with same
output level or PWM
Read port P0 output level or PWM
Write ports P0–P3 with same
output level or PWM
Read port P0 output level or PWM
Write ports P4–P7 with same
output level or PWM
Read port P4 output level or PWM
Write ports P8 or P9 with same
output level or PWM
Read port P8 output level or PWM
Read ports P7–P0 inputs
Read ports P9 and P8 inputs
Configuration
Ramp-down
Ramp-up
Output current ISET70
Output current ISET98
Global current
Factory reserved; do not write to
this register
ADDRESS
CODE
(HEX)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x7D
AUTO-
INCREMENT
ADDRESS
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x10
0x10
0x10
0x10
0x10
0x0F
0x0E
0x11
0x12
0x13
0x14
0x15
0x10
_______________________________________________________________________________________
7
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