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参数资料
| 型号： | MAX6946ATE+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 4/24页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVER LINEAR 16-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 恒定电流： | 是 |
| 拓扑： | 开路漏极，PWM |
| 输出数： | 10 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光 |
| 类型 - 次要： | RGB，白色 LED |
| 频率： | 400kHz |
| 电源电压： | 2.25 V ~ 3.6 V |
| 输出电压： | 7V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 供应商设备封装： | 16-TQFN（3x3） |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 125°C |
10-Port, Constant-Current LED Driver and
I/O Expander with PWM Intensity Control
TIMING CHARACTERISTICS (Figure 8)
(V DD = 2.25V to 3.6V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V DD = 3.3V, T A = +25°C.) (Note 1)
PARAMETER
Internal PWM Clock Frequency
SYMBOL
f INT
CONDITIONS
16-pin TQFN
16-bump WLP
MIN
23
20
TYP
32
32
MAX
42
45
UNITS
kHz
External PWM Clock Frequency
Serial-Clock Frequency
Bus Free Time Between a STOP and
a START Condition
Hold Time, (Repeated) START
Condition
Repeated START Condition Setup
Time
STOP Condition Setup Time
f OSC
f SCL
t BUF
t HD, STA
t SU, STA
t SU, STO
1.3
0.6
0.6
0.6
100
400
kHz
kHz
μs
μs
μs
μs
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
t HD, DAT
t SU, DAT
t LOW
t HIGH
(Note 3)
180
1.3
0.7
0.9
μs
ns
μs
μs
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmitting
t R
t F
t F, TX
(Notes 4, 5)
(Notes 4, 5)
(Notes 4, 6)
20
+ 0.1C b
20
+ 0.1C b
20
+ 0.1C b
300
300
250
ns
ns
ns
Pulse Width of Spike Supressed
Capacitive Load for Each Bus Line
t SP
C b
(Note 7)
(Note 4)
50
400
ns
pF
RST Pulse Width
RST Rising Edge to
t W
Reset Run enabled,
16-pin TQFN
0.1
3.0
μs
MAX6946/MAX6947 ACK to Cancel
t RSTRUN
internal oscillator
ms
Reset Run
enabled
16-bump WLP
2.5
RST Rising Edge to
MAX6946/MAX6947 ACK to Ensure
Reset Run
t RSTRUN
Reset Run enabled, internal oscillator
enabled
5.6
ms
Note 1: All parameters are tested at T A = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Port current is factory trimmed to meet a median sink current of 20mA and 10mA over all ports. The Δ I OUT specification
guarantees current matching between parts.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V IL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 4: Not production tested. Guaranteed by design.
Note 5: C b = total capacitance of one bus line in picoFarads; tR and tF are measured between 0.3 x V DD and 0.7 x V DD .
Note 6: I SINK ≤ 6mA.
Note 7: Guaranteed by design. Input filters on the SDA and SCL inputs suppress noise spikes of less than 50ns.
4
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