参数资料
型号: MAX6950CEE+T
厂商: Maxim Integrated
文件页数: 3/19页
文件大小: 0K
描述: IC DRVR DSPL LED SRL 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
显示器类型: LED
配置: 7 段显示
接口: 3 线串口
数字或字符: 5 位数字
电流 - 电源: 10mA
电源电压: 2.7 V ~ 5.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-LSSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP 裸露焊盘
包装: 带卷 (TR)
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
ELECTRICAL CHARACTERISTICS
(Typical operating circuit, V+ = +3.0V to +5.5V, T A = T MIN to T MAX , unless otherwise noted.) (Note 1)
PARAMETER
Slow Segment Blink Period
(Internal Oscillator)
Fast Segment Blink Period
(Internal Oscillator)
Fast or Slow Segment Blink Duty
Cycle (Note 2)
Digit Drive Sink Current
Segment Drive Source Current
SYMBOL
f SLOWBLINK
f FASTBLINK
I DIGIT
I SEG
CONDITIONS
Eight digits scanned, OSC = RC oscillator,
R SET = 56k ? , C SET = 27pF
Eight digits scanned, OSC = RC oscillator,
R SET = 56k ? , C SET = 27pF
T A = +25°C, V LED = 2.4V
T A = +25°C, V LED = 2.4V
MIN
49.9
240
-30
TYP
1
0.5
50
320
-40
MAX
50.1
400
-50
UNITS
s
s
%
mA
mA
Digit Drive Sink Current (Note 2)
Segment Drive Source Current
(Note 2)
Slew Rate Rise Time
I DIGIT
I SEG
? I SEG / ? t
T A = +25°C, V+ = 2.7V to 3V, V LED = 2.2V
T A = +25°C, V+ = 2.7V to 3V, V LED = 2.2V
T A = +25°C
80
-10
35
mA
mA
mA/μs
LOGIC INPUTS
Input Current DIN, CLK, CS
I IH , I IL
V IN = 0 or V+
-2
2
μA
Logic High Input Voltage DIN,
CLK, CS
Logic Low Input Voltage DIN,
CLK, CS
Hysteresis Voltage DIN, CLK, CS
V IH
V IL
? V I
2.4
0.5
0.4
V
V
V
TIMING CHARACTERISTICS (Figure 1)
CLK Clock Period
CLK Pulse Width High
CLK Pulse Width Low
CS Fall to CLK Rise Setup Time
CLK Rise to CS Rise Hold Time
DIN Setup Time
DIN Hold Time
CS Pulse High
t CP
t CH
t CL
t CSS
t CSH
t DS
t DH
t CSW
38.4
19
19
9.5
3
9.5
0
19
ns
ns
ns
ns
ns
ns
ns
ns
TIMING CHARACTERISTICS (V+ = +2.7V) (Note 2)
CLK Clock Period
CLK Pulse Width High
CLK Pulse Width Low
CS Fall to CLK Rise Setup Time
CLK Rise to CS Rise Hold Time
DIN Setup Time
DIN Hold Time
CS Pulse High
t CP
t CH
t CL
t CSS
t CSH
t DS
t DH
t CSW
50
24
24
12
4
12
4
24
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: All parameters tested at T A = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
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