参数资料
型号: MAX6955AAX+T
厂商: Maxim Integrated
文件页数: 7/43页
文件大小: 0K
描述: IC DRVR DSPL LED 36-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1,000
显示器类型: LED
配置: 7、14、16 段
接口: I²C
电流 - 电源: 22mA
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 36-BSOP(0.295",7.50mm 宽)
供应商设备封装: 36-SSOP
包装: 带卷 (TR)
MAX6955
2-Wire Interfaced, 2.7V to 5.5V LED Display
Driver with I/O Expander and Key Scan
1a
2a
a
a1
a2
1f
1b
2f
2b
f
h
i
j
b
f
h
i
j
b
1g
2g
g1
g2
g1
g2
1e
1c
2e
2c
e
m
l
k
c
e
m
l
k
c
1dp
2dp
dp
dp
1d
2d
d
d2
d1
Figure 1. Segment Labeling for 7-Segment Display, 14-Segment Display, and 16-Segment Display
Table 1. MAX6955 Drive Capability
DISPLAY TYPE
Monocolor
Bicolor
7 SEGMENT
(16-CHARACTER
HEXADECIMAL FONT)
16
8
14 SEGMENT/
16 SEGMENT
(104-CHARACTER ASCII FONT MAP)
8
4
DISCRETE LEDs
(DIRECT CONTROL)
128
64
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX6955, and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX6955 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7k ? ,
is required on the SDA. The MAX6955 SCL line oper-
ates only as an input. A pullup resistor, typically 4.7k ? ,
is required on SCL if there are multiple masters on the
2-wire interface, or if the master in a single-master sys-
tem has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX6955
7-bit slave address plus R/ W bit (Figure 4), a register
address byte, 1 or more data bytes, and finally a STOP
condition (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Maxim Integrated
Bit Transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 5).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data (Figure 6).
Thus, each byte transferred effectively requires 9 bits. The
master generates the 9th clock pulse, and the recipient
pulls down SDA during the acknowledge clock pulse, such
that the SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the
MAX6955, the MAX6955 generates the acknowledge bit
because the MAX6955 is the recipient. When the MAX6955
is transmitting to the master, the master generates the
acknowledge bit because the master is the recipient.
Slave Address
The MAX6955 has a 7-bit-long slave address (Figure
4). The eighth bit following the 7-bit slave address is the
R/ W bit. It is low for a write command, high for a read
command.
The first 3 bits (MSBs) of the MAX6955 slave address
are always 110. Slave address bits A3, A2, A1, and A0
are selected by the address input pins AD1 and AD0.
These two input pins can be connected to GND, V+,
SDA, or SCL. The MAX6955 has 16 possible slave
addresses (Table 5) and therefore a maximum of 16
MAX6955 devices can share the same interface.
7
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